Patents Examined by Joseph D. Torres
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Patent number: 12292473Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.Type: GrantFiled: December 4, 2023Date of Patent: May 6, 2025Assignee: Google LLCInventors: Andreas Georg Nowatzyk, Olivier Temam
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Patent number: 12277288Abstract: An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device.Type: GrantFiled: June 26, 2023Date of Patent: April 15, 2025Assignee: Silicon Motion, Inc.Inventor: Fu-Jen Shih
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Patent number: 12273127Abstract: An Error correction code (ECC) decoder including an input manager configured to sequentially receive a first read data including a plurality of data units read from a plurality of sectors in a memory cell array of a nonvolatile memory device, by unit of sector, a pre-decoder configured to sequentially receive the first read data and generate a respective syndrome of each of the data units, and a main decoder configured to sequentially perform a first ECC decoding on the first read data based on the respective syndrome. The input manager includes a defective sector buffer to store a data unit having a minimum expected error count from among data units on which a first ECC decoding is failed. The main decoder performs a second ECC decoding on a defective data unit stored in the defective sector buffer and receives a second read data from a selected sector corresponding to the defective data unit.Type: GrantFiled: July 5, 2023Date of Patent: April 8, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jaehun Jang, Mankeun Seo, Hongrak Son, Bohwan Jun
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Patent number: 12267210Abstract: Technologies for optimizing post-FEC bit error rate performance of a Forward Error Correction (FEC) system are described. A controller is coupled to an FEC circuit and a receiver circuit. The controller receives FEC symbol error data from the FEC circuit and determines, using the FEC symbol error data, a post-FEC correlated performance metric indicative of an estimated post-FEC BER of the FEC circuit. The controller adjusts, based on the post-FEC correlated performance metric, at least one of a FEC parameter of the FEC circuit or a link parameter of the receiver circuit to decrease the estimated post-FEC BER. This improves the post-FEC BER performance of the FEC circuit.Type: GrantFiled: February 21, 2023Date of Patent: April 1, 2025Assignee: NVIDIA CorporationInventors: Pervez Mirza Aziz, Vishnu Balan, Rohit Rathi
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Patent number: 12267159Abstract: There are provided a channel coding method, a processing device, a communication method and a device. The channel coding method includes: using a generating matrix or a check matrix of QC-LDPC codes to channel-encode or channel-decode a code stream, wherein a code rate of the generating matrix or the check matrix is 1/6, 1/4 or 1/3. The method can be used in a transmission environment with a low signal-noise ratio and a long distance.Type: GrantFiled: February 17, 2023Date of Patent: April 1, 2025Assignees: Beijing ESWIN Computing Technology Co., Ltd., Guangzhou Transa Semi Information Technology Co., Ltd.Inventors: Yanqi Wu, Yanzhong Dai, Sujiang Rong
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Patent number: 12267198Abstract: A first wireless communication device configured to encode real samples of data to obtain encoded data based at least in part on adding one or more time domain complex samples to the real samples of the data, wherein a function of the one or more time domain complex samples is a known value, and wherein the function is a sum of exponentials of the one or more time domain complex samples. The first wireless communication device is configured to transmit, to a second wireless communication device, the encoded data.Type: GrantFiled: April 19, 2024Date of Patent: April 1, 2025Assignee: QUALCOMM IncorporatedInventors: Ori Shental, Meilong Jiang, Ashwin Sampath, Ahmed Bedewy
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Patent number: 12250008Abstract: A method for serializing communications in the computing field includes serializing input data into a serialized stream of symbols, based on one or more encodings, at a serializer, each symbol including a disparity code selected based on a running disparity (RD) of the serialized stream of symbols. The running disparity (RD) is tracked by setting the RD to an initial value, and then adding a disparity of each symbol to the RD to ensure the RD does not exceed a desired maximum, e.g., three. A positive disparity encoding or a negative disparity encoding of each symbol is selected for transmission based on the RD. The serialized data stream of symbols is transmitted along a data conduit, to a deserializer, in which the serialized data stream of symbols is deserialized to determine a corresponding bit value, for outputting decoded information in parallel form.Type: GrantFiled: May 4, 2023Date of Patent: March 11, 2025Assignee: Luminous Computing, Inc.Inventors: Ben Melton, Dave Baker
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Patent number: 12244326Abstract: A FEC codec for generating a check byte for a message. The FEC codec includes a port encoder having a storage unit, a Galois field multiplier, and a sum unit. The storage unit stores a first staged result, which is accumulated based on previous sets of input byte of the message for all clock cycles from a first clock cycle to a clock cycle immediately prior to the current clock cycle. The Galois field multiplier performs a Galois field multiplication of the first staged result and a power of the alpha to generate a Galois field product. The sum unit performs a Galois field addition on an internal input based on a consolidated byte for the current clock cycle and the Galois field product to generate a second staged result for subsequent use to generate the check byte. Other embodiments may be described and/or claimed.Type: GrantFiled: July 19, 2023Date of Patent: March 4, 2025Assignee: Intel CorporationInventors: Debendra Das Sharma, Swadesh Choudhary
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Patent number: 12238036Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) determine that at least one packet of a set of packets for a downlink message is unsuccessfully received at a radio link control (RLC) layer of the UE due to a specific situation of a set of specific situations and may transmit the NACK message based on the missing packet (s) on an as needed basis rather than waiting for a timer to expire (e.g., a fast NACK mechanism). In some examples, the specific situations may include the UE missing packets after a measurement gap, missing packets based on wake up latencies for a discontinuous reception mode of the UE, missing packets due to interference from reference signals transmitted by neighboring cells, missing packets due to the UE not decoding retransmissions that have a same redundancy version (RV) of a downlink message, or a combination thereof.Type: GrantFiled: February 11, 2021Date of Patent: February 25, 2025Assignee: QUALCOMM IncorporatedInventors: Sitaramanjaneyulu Kanamarlapudi, Ling Xie, Hobin Kim, Leena Zacharias, Wei Li
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Patent number: 12236319Abstract: A quantum error correcting code with dynamically generated logical qubits is provided. When viewed as a subsystem code, the code has no logical qubits. Nevertheless, the measurement patterns generate logical qubits, allowing the code to act as a fault-tolerant quantum memory. Each measurement can be a two-qubit Pauli measurement.Type: GrantFiled: June 30, 2021Date of Patent: February 25, 2025Assignee: Microsoft Technology Licensing, LLCInventors: Matthew Hastings, Jeongwan Haah
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Patent number: 12238194Abstract: Systems and methods are described that enable user terminals to eliminate or reduce the number of dummy bursts (or bursts with no data) they send. The systems and methods use two burst detectors, a first burst detector that analyzes the physical structure of the signal, and a second burst detector that analyzes the informational structure of the signal. Output from the first burst detector can be used to control operation of a signal decoder that decodes received signals. The second burst detector analyzes output from the signal decoder to determine the second burst indicator. In other words, the first burst detector can be implemented prior to decoding the received signal to provide a first estimate related to the presence or absence of a burst. This can then be used to limit the amount of processing performed by the signal decoder.Type: GrantFiled: April 6, 2021Date of Patent: February 25, 2025Assignee: VIASAT, INC.Inventors: Kaushik Chakraborty, Srikar Potta, Aniruddha Das, James E. Petranovich
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Patent number: 12229024Abstract: Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.Type: GrantFiled: March 18, 2024Date of Patent: February 18, 2025Assignee: MICRON TECHNOLOGY, INC.Inventors: Robert Mason, Scott A. Stoller, Pitamber Shukla, Kenneth W. Marr, Chi Ming Chu, Hossein Afkhami
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Patent number: 12231148Abstract: A method of simplified successive cancellation list (SSCL) error decoding of S-polar codes includes representing an S-polar code as a perfect binary tree; providing a node v a vector ?v(l) of soft information from a parent node; computing a vector ?vl(l) of soft information for a left child of node v; providing node v with a vector ?vl(l) of hard decisions from the left child and using it with ?v(l) to create a soft information vector ?vr(l) and passing it to a right child of node v; providing node v with a vector ?vr(l) of hard decisions from its right child and using it with ?vl(l) to create a hard decision vector, ?v of hard decisions, and passing it to its parent node; updating, when v is a ith leaf of the perfect tree, two path metrics, and selecting paths obtained by expanding current paths with a lowest path metric.Type: GrantFiled: November 16, 2023Date of Patent: February 18, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Amit Berman, Sarit Buzaglo, Ariel Doubchak
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Patent number: 12224772Abstract: In a compression mode in which plaintext data is input, and compressed, a first code that is an error detection code is generated with respect to the plaintext data, and compressed. A circuit generates restored plaintext data in which the compressed data is decompressed, for confirming successfulness. A second code that is an error detection code is generated with respect to the restored plaintext data and is compared with the first code. In a case where the first code and the second code agree, the compressed data and the first or second code are output. In a decompression mode, plaintext data is generated in which the input compressed data is decompressed. A third code that is an error detection code is generated with respect to the plaintext data and is compared with an input code, and when the input code and the third code agree, the plaintext data is output.Type: GrantFiled: March 23, 2023Date of Patent: February 11, 2025Assignee: HITACHI VANTARA, LTD.Inventors: Tomoyuki Kamazuka, Kenshiro Himoto, Shoji Kato, Yuusaku Kiyota
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Patent number: 12212339Abstract: An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.Type: GrantFiled: November 10, 2022Date of Patent: January 28, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myungkyu Lee, Kijun Lee, Sunghye Cho, Sungrae Kim
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Patent number: 12203981Abstract: A diagnostic device includes a probe, a motor configured to scan the probe over a test circuit, a superconducting quantum interference device (SQUID) attached to the probe and configured to be coupled to the test circuit such that an electronic noise present in the test circuit induces a first current that flows through the SQUID, and a current path configured to receive a second current that flows through the SQUID. The SQUID is configured to generate an output in a form of a first voltage in response to a sum of the first current and the second current being less than a threshold current, and a second voltage in response to the sum of the first current and the second current being greater than the threshold current.Type: GrantFiled: June 15, 2023Date of Patent: January 21, 2025Assignee: The Boeing CompanyInventors: Ian M. Dayton, Mark Edward Nowakowski
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Patent number: 12199764Abstract: A system and a method performed by a source node for communicating data packets in the network comprising dividing a payload for data transmission into a plurality of source chunks with each source chunk comprising a significance level; performing, according to the significance level of each of the plurality of source chunks, adaptive network coding on each source chunk to obtain a plurality of coded chunks in a plurality of coding groups, where a significance level of coded chunks in at least two of the plurality of the coding groups is different, and wherein each coding group of the plurality of coding groups comprises at least one coded chunk having the same first significance level; generating a first coded data packet comprising a header and a payload comprising the plurality of coded chunks; and transmitting the first coded data packet to a destination node.Type: GrantFiled: June 6, 2023Date of Patent: January 14, 2025Assignee: Huawei Technologies Co., Ltd.Inventor: Lijun Dong
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Patent number: 12188983Abstract: A method and system for controlling actions of testbench components present within a test environment based on a testing context is disclosed. In some embodiments, the method includes receiving a controllable actions packet from each of a plurality of testbench components in the test environment; parsing a testing context associated with a test sequence; generating a context-based actions control packet for each of the plurality of testbench components, based on the testing context metadata and the list of controllable actions corresponding to each of the plurality of testbench components; and transmitting the context-based actions control packet to an associated testbench component of the plurality of testbench components.Type: GrantFiled: June 14, 2023Date of Patent: January 7, 2025Inventors: Manickam Muthiah, Karthikeyan Keelapandal Sundaram, Nisha Ravichandran, Sathish Kumar Krishnamoorthy, Razi Abdul Rahim
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Patent number: 12191883Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.Type: GrantFiled: June 1, 2023Date of Patent: January 7, 2025Assignee: QUALCOMM IncorporatedInventors: Shrinivas Kudekar, Thomas Joseph Richardson
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Patent number: 12190988Abstract: A data coding device may include a raw data storage configured to store raw data of which the total number of bits is 2N, a previous data storage configured to store previous data output before the raw data, a counter configured to count the number of reference data bits included in the raw data, and a data output circuit configured to invert and output the raw data according to a comparison result with the previous data when the number of reference data bits included in the raw data is N, and invert and output the raw data according to the number of reference data bits included in the raw data when the number of reference data bits included in the raw data is not N.Type: GrantFiled: January 9, 2023Date of Patent: January 7, 2025Assignee: SK hynix Inc.Inventors: Ie Ryung Park, Dong Sop Lee