Patents Examined by Joseph D. Torres
  • Patent number: 10819371
    Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 3/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: October 27, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 10812106
    Abstract: The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: October 20, 2020
    Assignee: SONY CORPORATION
    Inventors: Yuji Shinohara, Makiko Yamamoto
  • Patent number: 10810098
    Abstract: A first processing component samples and lossily accumulates statistical activity data by generating at least one data bucket by segmenting a memory window in a memory and providing a map of the segmented memory window; sampling to detect activity in the data bucket and surjectively populating the map with statistical activity data; and responsive to a trigger, passing at least part of a population of the map to a second processing component. The second processing component receives and stores the at least part of the population of the surjective map, compares it with at least one previously stored map population; and on detecting anomalous patterning, performs an “anomaly detected” action.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: October 20, 2020
    Assignee: Arm IP Limited
    Inventors: Milosch Meriac, Thomas Christopher Grocutt, Jonathan Michael Austin, Geraint David Luff
  • Patent number: 10811116
    Abstract: A semiconductor system may be configured to classify failure groups of data including erroneous bits and may replace a memory area in which the failure groups are stored with a redundancy area. The replacement of the memory area in which the failure groups are stored, with the redundancy area, may be performed according to priorities of the failure groups.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: October 20, 2020
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Sangkwon Lee
  • Patent number: 10789117
    Abstract: Embodiments of ensuring data integrity in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving, at a memory controller, a data request from the persistent storage to copy data from the memory. In response to the received data request, the requested data is retrieved from the memory. The retrieved data contains data bits and corresponding error correcting bits. The method can also include determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits associated with the data bits. In response to determining that the retrieved data bits contain one or more data integrity errors, the memory controller can write data representing existence of the one or more data integrity errors into a memory location accessible by the processor for ensuring data integrity.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: September 29, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bryan Kelly, Mallik Bulusu, Tom Nguyen
  • Patent number: 10784986
    Abstract: Aspects of the embodiments are directed to systems, methods, and devices that can activate forward error correction (FEC) based on the channel loss of a channel. The channel's loss can be characterized as a high loss channel if the channel loss exceeds a predetermined threshold value. For channels with high loss and for those that operate at high data rates (e.g., data rates commensurate with PCIe Gen 4 or Gen 5), FEC can be activated so that the channels can achieve higher data rates.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventor: Debendra Das Sharma
  • Patent number: 10775435
    Abstract: Exemplary embodiments of the present disclosure relate to a clock distribution network for a scan design, which may include, for example, a clock signal network(s), and a plurality of partitioned clock signal networks coupled to the clock signal network(s) through a controlling logic(s); where the controlling logic(s) may be configured to stagger a clock signal from the clock signal network(s), and where each of the partitioned clock signal networks may be connected to a group of flip-flops. A first partitioned clock signal network of the partitioned clock signal networks may be connected to a first group of flip-flops and a second partitioned clock signal network of the partitioned clock signal networks may be connected to a second group of flip-flops, and where the first group of flip-flops may be different than the second group of flip-flops. The controlling logic(s) may include a shift register(s).
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: September 15, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Christos Papameletis, Brian Edward Foutz, Vivek Chickermane, Krishna Vijaya Chakravadhanula
  • Patent number: 10763897
    Abstract: A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a memory region within the host and read the data from the memory region within the host. The controller includes a first encoding/decoding circuit configured to execute encoding/decoding with a first encoding scheme, a second encoding/decoding circuit configured to execute encoding/decoding with a second encoding scheme having a higher error correcting capability than an error correcting capability of the first encoding scheme, an encoding scheme selecting circuit configured to select an encoding/decoding circuit from the first encoding/decoding circuit and the second encoding/decoding circuit to perform encoding of data to be stored in the memory region, based on information about the data read from the memory region.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kenji Funaoka, Takuya Haga, Toru Katagiri, Konosuke Watanabe
  • Patent number: 10763898
    Abstract: A memory system includes a nonvolatile semiconductor memory and a controller. The controller is configured to maintain a plurality of log likelihood ratio (LLR) tables for predicting a value of data read from the nonvolatile semiconductor memory, count a number of times that each of write operations, erase operations, and read operations have been carried out with respect to each unit storage region of the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on the counted number of the read operations and one of the counted number of the write operations and the counted number of the erase operations, which correspond to a target unit storage region of a read operation, and carry out decoding of data read from the target unit storage region of the read operation, using one of the LLR tables selected according to the determined order.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takuya Haga
  • Patent number: 10761917
    Abstract: A method begins with a processing module of a dispersed storage network (DSN) receiving a first data object for storage in the DSN from a requesting entity based on an identifier associated with the first data object. The method continues with the processing module storing the first data object in the DSN, facilitating storage of the first data object in a cache memory using an address-based map and determining whether to transfer one or more data objects of a plurality of data objects from the cache memory. Based on a determination to transfer one or more data objects, the method continues by identifying a data object and another processing module to receive the data object, initiating a capacity query for the other processing module. The method continues with the processing module facilitating transfer of the second data object to the other processing module, receiving a transfer confirmation message; and facilitating updating the address-based map.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 1, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: S. Christopher Gladwin, Jason K. Resch
  • Patent number: 10749632
    Abstract: An apparatus for smart integrated cyclic data transport is provided. The apparatus may preserve the consistency and integrity of a file during the transfer of the file from a source system to a target system. The apparatus includes an orchestration subsystem. The orchestration subsystem includes an analyzer/generator module. The analyzer/generator module executes an algorithm on the file at the source location. An output is generated from the executed algorithm. The apparatus includes a consistency module. The consistency module pre-checks the output at the source location for pretransfer validation and creates a copy of the output. The copy may preserve the consistency and the integrity of the file. The apparatus includes a data transfer subsystem which transfers the file and the output from the source system to the target system. The apparatus may also include a validation subsystem for validating the integrity and consistency of the file.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: August 18, 2020
    Assignee: Bank of America Corporation
    Inventors: Manu Kurian, Sorin Cismas, Jay Varma, Paul Grayson Roscoe, Balaji Subramanian, Himabindu Keesara, Nathan Allen Eaton, Jr., Vibhuti Damania
  • Patent number: 10741256
    Abstract: A data storage system may include a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device. Methods are also described.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: August 11, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mohsen Purahmad, Chao-Han Cheng, Dongxiang Liao, Bo Lei
  • Patent number: 10732855
    Abstract: A storage system includes a storage device including a controller and a nonvolatile memory unit, and a host including a processor configured to determine whether or not the host is going to access the storage device within a predetermined range of time, and cause the storage device to be powered off when it is determined that the host is not going to access the storage device within the predetermined range of time.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: August 4, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Daisuke Hashimoto
  • Patent number: 10735032
    Abstract: A method includes: generating a trellis; generating one or more predicted symbols using a first non-linear model; computing and saving two or more branch metrics using a priori log-likelihood ratio (LLR) information, a channel observation, and the one or more predicted symbols; if alpha forward recursion has not yet completed, generating alpha forward recursion state metrics using a second non-linear model; if beta backward recursion has not yet completed, generating beta backward recursion state metrics using a third non-linear model; if sigma forward recursion has not yet completed, generating sigma forward recursion state metrics using the branch metrics, the alpha state metrics, and the beta backward recursion state metrics; generating extrinsic information comprising a difference of a posteriori LLR information and the a priori LLR information; computing and feeding back the a priori LLR information; and calculating the a posteriori LLR information.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: August 4, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventor: Daniel N. Liu
  • Patent number: 10725854
    Abstract: A disk device includes a disk medium, a magnetic recording head, a processor configured to control the magnetic recording head to write data to and read data from a plurality of tracks of the disk medium on a sector-by-sector basis, and a check value generation circuit configured to generate, for each of the plurality of tracks, check value data based on data stored in one or more sectors of the track. The processor controls the magnetic recording head to write check value data for a first track of the plurality of tracks in a first sector on the disk medium and check value data for a second track of the plurality of tracks in a second sector on the disk medium that is adjacent to the first sector.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: July 28, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Norikatsu Toukairin
  • Patent number: 10727875
    Abstract: An encoder and decoder using LDPC-CC which avoid lowering the transmission efficiency of information while not deteriorating error correction performance, even at termination; and an encoding method of the same. A termination sequence length determining unit determines the sequence length of a termination sequence transmitted added to the end of an information sequence, according to the information length (information size) and encoding rate of the information sequence. A parity calculation unit carries out LDPC-CC coding on the information sequence and the known-information sequence necessary for generating a termination sequence of the determined termination sequence length, and calculates a parity sequence.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: July 28, 2020
    Assignee: Panasonic Corporation
    Inventors: Yutaka Murakami, Hisao Koga, Nobutaka Kodama
  • Patent number: 10725528
    Abstract: Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: July 28, 2020
    Assignee: Altera Corporation
    Inventors: Shiva Rao, David Alexander Munday
  • Patent number: 10721033
    Abstract: According to one embodiment, a wireless communication apparatus includes controlling circuitry and transmitter circuitry. The controlling circuitry is configured to divide data into bit strings by a unit of a first number of bits; add at least one padding bit to one of the bit strings according to a difference between a number of bits of the one of the bit strings and the first number of bits, when the one of the bit strings has a number of bits less than the first number of bits; add error correction codes to the bit strings to generate encoded blocks, wherein each of the error correction codes has a second number of bits; combine the encoded blocks to generate encoded frames; and aggregate the encoded frames to generate a transmission packet. The transmitter circuitry is configured to transmit the transmission packet.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: July 21, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kentaro Taniguchi, Toshihisa Nabetani, Ryota Sekiya
  • Patent number: 10719393
    Abstract: According to one embodiment, a memory system copies content of a first logical-to-physical address translation table corresponding to a first region of a nonvolatile memory to a second logical-to-physical address translation table corresponding to a second region of the nonvolatile memory. When receiving a read request specifying a logical address in the second region, the memory system reads a part of the first data from the first region based on the second logical-to-physical address translation table. The memory system detects a block which satisfies a refresh condition from a first group of blocks allocated to the first region, corrects an error of data of the detected block and writes the corrected data back to the detected block.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: July 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Kanno
  • Patent number: 10719269
    Abstract: There are provided a memory controller, a memory system including the memory controller, and a method of operating the memory controller. In a memory controller for accessing a plurality of memories in response to a request from a host, the memory controller includes: a processor for generating a command set, based on command generation information of a selected memory among the plurality of memories; and a storage circuit for storing command generation information of each of the plurality of memories.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: July 21, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong Yeob Chun