Patents Examined by Joseph D. Torres
  • Patent number: 11152959
    Abstract: Systems and methods are disclosed for performing polar encoding of a number of information bits for transmission in a wireless communication system in a manner that is optimized for a specific code length. In some embodiments, a method of operation of a transmit node in a wireless communication system comprises performing polar encoding of a set of K information bits to thereby generate a set of polar-encoded information bits where the K information bits are mapped to the first K information bit locations specified in an information sequence SN which is a ranked sequence of N information bit locations among a plurality of input bits for the polar encoding where N is equivalent to a code length, a size of the information sequence SN is greater than or equal to K, and the information sequence SN is optimized for a specific value of the code length N.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: October 19, 2021
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Dennis Hui, Leefke Grosjean
  • Patent number: 11152957
    Abstract: Methods, systems and devices for forward error correction in orthogonal time frequency space (OTFS) communication systems using non-binary low-density parity-check (NB-LDPC) codes are described. One exemplary method for forward error correction includes receiving data, encoding the data via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, modulating the encoded data to generate a signal, and transmitting the signal. Another exemplary method for forward error correction includes receiving a signal, demodulating the received signal to produce data, decoding the data via a NB-LDPC code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, and providing the decoded data to a data sink.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: October 19, 2021
    Assignee: Cohere Technologies, Inc.
    Inventors: Vamadevan Namboodiri, Ronny Hadani, Stuart Abrams
  • Patent number: 11153032
    Abstract: Aspects of the embodiments are directed to systems, methods, and devices that can activate forward error correction (FEC) based on the channel loss of a channel. The channel's loss can be characterized as a high loss channel if the channel loss exceeds a predetermined threshold value. For channels with high loss and for those that operate at high data rates (e.g., data rates commensurate with PCIe Gen 4 or Gen 5), FEC can be activated so that the channels can achieve higher data rates.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventor: Debendra Das Sharma
  • Patent number: 11146292
    Abstract: A data decoder includes a communication unit receiving a bit signal with encoded data; a first operation unit that bit shifts the bit signal by a first length, corresponding to a length of a spreading code used to encode the data, to generate a first operation stream; a second operation unit generating a second operation stream without the spreading code; a third operation unit that bit shifts the second operation stream by a second length to generate a third operation stream; a fourth operation unit generating a fourth operation stream from which the data is removed using the second operation stream and the third operation stream; and a polynomial generator that decodes the encoded data using the fourth operation stream.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 12, 2021
    Inventors: Cheolsun Park, Chiho Lee, Unseob Jeong, Dongyeong Kim, Junghwan Song, Dongweon Yoon
  • Patent number: 11146296
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, an encoding device may determine a least reliable subset of information bits included in a set of information bits that includes a predefined active set of information bits to be encoded; may determine a codeword bit to be added to a codeword based at least in part on the least reliable subset of information bits, wherein adding the codeword bit to the codeword improves reliability of the least reliable subset of information bits; may add the codeword bit to the codeword; and may transmit the codeword. Numerous other aspects are provided.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: October 12, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Kai Chen, Changlong Xu, Liangming Wu, Jing Jiang, Hao Xu
  • Patent number: 11133894
    Abstract: The present disclosure relates to information transmission method, decoding method, and apparatus. One example method includes encoding, by a sending device, a to-be-encoded sequence based on preset parameters to obtain an encoded sequence, where the preset parameters include a quantity of check bits, positions of the check bits, and a check equation, and sending the encoded sequence to a receiving device.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: September 28, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Huazi Zhang, Rong Li, Yunfei Qiao, Hejia Luo, Gongzheng Zhang, Ying Chen
  • Patent number: 11128401
    Abstract: This application discloses a method and an apparatus for processing information, a communications device, and a communications system. The communications device is configured to obtain a starting position of an output bit sequence in a coded block in a circular buffer, and determine the output bit sequence in the coded block based on a length of the output bit sequence and the starting position. A value of the starting position is one of {p0, p1, p2 . . . , pkmax?1}, where 0?pk<NCB, Pk is an integer, k is an integer, 0?k<kmax, NCB is a size of the coded block, and kmax is an integer greater than or equal to 4.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: September 21, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Liang Ma, Xin Zeng, Yuejun Wei, Carmela Cozzo
  • Patent number: 11115059
    Abstract: An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit strings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: September 7, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Kazumasa Mikami, Junichi Sugiyama
  • Patent number: 11101823
    Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: August 24, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Yasuyuki Imaizumi, Satoshi Shoji, Mitsunori Tadokoro, Takashi Ishiguro, Yifan Tang
  • Patent number: 11095420
    Abstract: Techniques are disclosed relating to preemption indicators in the context of multiplexing different services on wireless physical layer frames. In some embodiments, a preemption indication is transmitted to indicate resources used by a preempting transmission. The preemption indication may be used when preemption is enabled, e.g., as indicated by an RRC message. The preemption indication may be common to multiple UEs. The resources used by the preempting transmission may overlap with other transmissions. In various embodiments, the disclosed techniques may facilitate signal preemption, e.g., by a low-latency, high-reliability data service.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: August 17, 2021
    Assignee: Apple Inc.
    Inventors: Yuchul Kim, Wei Zeng, Xiangying Yang, Haijing Hu, Dawei Zhang
  • Patent number: 11095308
    Abstract: A check node processing unit configured to determine check node messages to decode a signal encoded using NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units configured to determine permuted variable node messages by permuting variable node messages generated by one or more variable node processing units; a syndrome sub-check node configured to determine check node messages from a set of syndromes, the set of syndromes being determined from one or more intermediate messages computed from the permuted variable node messages; a forward-backward sub-check node configured to determine permuted check node messages from the intermediate messages; a switching unit configured to generate check node messages of given index from the check node messages or from the permuted check node messages depending on the giving index.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: August 17, 2021
    Assignee: UNIVERSITE DE BRETAGNE SUD
    Inventors: Cédric Marchand, Emmanuel Boutillon
  • Patent number: 11086716
    Abstract: A method and apparatus for decoding are disclosed. The method includes receiving a first Forward Error Correction (FEC) block of read values, starting a hard-decode process in which a number of check node failures is identified and, during the hard-decode process comparing the identified number of check node failures to a decode threshold. When the identified number of check node failures is not greater than the decode threshold the hard-decode process is continued. When the identified number of check node failures is greater than the decode threshold, the method includes: stopping the hard-decode process prior to completion of the hard-decode process; generating output indicating that additional reads are required; receiving one or more additional FEC blocks of read values, mapping the first FEC block of read values and the additional FEC blocks of read values into soft-input values; and performing a soft-decode process on the soft-input values.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: August 10, 2021
    Assignee: Microchip Technology Inc.
    Inventor: Peter John Waldemar Graumann
  • Patent number: 11088713
    Abstract: A method for extending a polar code by determining an extension number E such that E/2<N<E whereby N is a number of codeword bits for a polar code that is to be extended and extending a codeword by adding additional redundant/extension bits. Information indicative of a bit unreliability associated with each bit in the codeword is accessed and bit positions with the highest unreliabilities are selected. Input data for an extended codeword is determined by adding a number of redundant bits in the respective selected bit positions.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: August 10, 2021
    Inventor: Diego Melloni
  • Patent number: 11088710
    Abstract: A memory controller configured to control a memory module, the memory controller including processing circuitry configured to perform ECC decoding on a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome, determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome, and output a decoding status flag indicating the type of error.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kijun Lee, Chanki Kim, Sunghye Cho, Myungkyu Lee
  • Patent number: 11082147
    Abstract: Provided are a processing method, device, and system for an overlapped multiplexing system. The method includes: receiving encoded information output by a transmit end, where the encoded information is information obtained by performing error-correcting code encoding and overlapped multiplexing encoding on input information; decoding the encoded information according to an overlapped multiplexing decoding algorithm, to obtain a first decoding result; performing error-correcting processing on the first decoding result according to an error-correcting code decoding algorithm, to obtain a second decoding result; and outputting the second decoding result.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: August 3, 2021
    Assignee: SHEN ZHEN KUANG-CHI HEZHONG TECHNOLOGY LTD
    Inventors: Ruopeng Liu, Chunlin Ji, Zihong Liu
  • Patent number: 11068345
    Abstract: In general, embodiments of the invention relate to storing data and managing the stored data in linked nodes. More specifically, embodiments of the invention relate to nodes linked together in a daisy chain configuration such as, but not limited to, a single-chain configuration and a dual-chain configuration, which use data protection domain (DPD) information to determine where and/or how to store the data.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: July 20, 2021
    Assignee: Dell Products L.P.
    Inventors: Rizwan Ali, Dharmesh M. Patel, Arvind Ramakrishnan Palamadai, Ravikanth Chaganti
  • Patent number: 11068341
    Abstract: A method for providing error correction for a memory array includes for each memory word stored in a data memory portion of the memory array having at least one bit error, storing in an error PROM error data identifying a memory address for the data word in the data memory portion, a bit position of each bit error, and correct bit data for each bit error, monitoring memory addresses presented to the data PROM, if a memory address presented to the data memory portion is an identified memory address, reading from the error PROM the bit position of each bit error and the correct bit data for each bit error, and substituting the correct bit data into each identified bit position of a sense amplifier reading data from the data memory portion.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: July 20, 2021
    Assignee: Microchip Technology Inc.
    Inventor: John L. McCollum
  • Patent number: 11063612
    Abstract: An encoder encodes input data utilizing a binary symmetry-invariant product code including D data bits and P parity bits in each dimension. The encoder includes a half-size data array including K subarrays each having multiple rows of storage for H bits of data, where D is an integer equal to 2×H+1 and K is an integer that is 2 or greater. The encoder is configured to access K rows of data by reading a respective H-bit data word of input data from each of the multiple subarrays and K H-bit data words of duplicate data from across multiple different rows of the subarrays. The encoder further includes at least one register configured to receive the bits read from the half-size data array code and rotate them as needed, at least one row parity generator, and a column parity generator that generates column parities based on row parity.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Robert Allan Cyprus, Charles Camp
  • Patent number: 11054471
    Abstract: A method includes receiving tester configuration data, test pattern data, and tester operation data; configuring a circuit for performing a designated test evaluation; generating a stimulus waveform; converting the stimulus waveform to an analog stimulus signal; transferring the analog stimulus signal to a first terminal of a MTJ DUT at reception of a trigger timing signal; generating time traces based on the trigger timing signal; generating a response signal at a second terminal of the MTJ DUT and across a termination resistor as the analog stimulus signal is transferred through the MTJ DUT; converting the response signal to a digitized response signal indicating its voltage amplitude; and performing the designated test evaluation and analysis function in the configurable circuit based on voltage amplitudes and time values of the stimulus waveform, the digitized response signal, and the timing traces.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guenole Jan, Huanlong Liu, Jian Zhu, Yuan-Jen Lee, Po-Kang Wang
  • Patent number: 11057051
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment may construct, for adjusted fractally enhanced kernel (FRANK) polar coding, encoding code for encoding data of an ultra-reliable low latency (URLLC) communication, wherein an information bit assignment to an information bit set associated with the encoding code is performed based at least in part on an adjusted dimensionality factor, wherein the encoding code is all-stage FRANK polar code or partial-stage FRANK polar code, and wherein the encoding code is constructed for code block shortening or code block puncturing. In some aspects, the user equipment may transmit the URLLC communication encoded using the encoding code based at least in part on the information bit assignment to the information bit set. Numerous other aspects are provided.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: July 6, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Ying Wang, Jing Jiang, Wei Yang, Gabi Sarkis, Jing Lei, Seyong Park