Patents Examined by Joseph D. Torres
  • Patent number: 11562281
    Abstract: Systems and methods that address an optimized method to handle portfolio constraints such as integer budget constraints and solve portfolio optimization problems that map both to mixed binary and quadratic binary optimization problems. A digital processor is used to create a hierarchical clustering; this clustering is leveraged to allocate capital to sub-clusters of the hierarchy. Once the sub-clusters are sufficiently small, a quantum processor is used to solve the portfolio optimization problem. Thus, the innovation employs clustering to reduce an optimization problem to sub-problems that are sufficiently small enough to be solved using a quantum computer given available qubits.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: January 24, 2023
    Inventors: Daniel Josef Egger, Stefan Woerner
  • Patent number: 11558168
    Abstract: Techniques are disclosed relating to downlink control information for wireless communications. In some embodiments, the downlink control information includes code block group information that indicates which code block groups are transmitted and soft buffer handling information that indicates whether to flush previously-determined soft bits that correspond to one or more code block groups.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: January 17, 2023
    Assignee: Apple Inc.
    Inventors: Yuchul Kim, Wei Zeng, Xiangying Yang, Haijing Hu, Dawei Zhang
  • Patent number: 11552736
    Abstract: The disclosed systems and methods for encoding, by a polar encoder, K message bits into an encoded message bits sequence C(M) using polar codes, where K and M are integer values and M is greater than or equal to K; rearranging, by an interleaver, the encoded message bits sequence C(M) to rearranged encoded message bits sequence C?(M) such that a C(i)th bit and a C ? ( M 2 + i ) th bit of the encoded message bits sequence C(M) are arranged together, where i is an integer value that varies between 1 to M 2 ; mapping, by a bits-to-symbol mapper, the rearranged encoded message bits sequence C(M) to N non-binary symbols, where N is an integer value; and processing, by a transmitter symbol processor, the N non-binary symbols to transmit the processed non-binary symbols towards a receiver.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: January 10, 2023
    Inventors: Hamid Ebrahimzad, Ali Farsiabi, Zhuhong Zhang
  • Patent number: 11551769
    Abstract: A one-time programmable (OTP) memory has a plurality of pages. A predefined section of each page is configured to store error policy bits. When an indicator in a first predefined location has a first value, the page is configured to store data with error correction code (ECC) bits, and when the indicator has a second value, at least a portion of the page is configured to store data with redundancy. Address translation circuitry is configured to, in response to receiving an access address, use a second predefined location of an accessed page of the plurality of pages accessed by the access address to determine a physical address in the accessed page which corresponds to the access address.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 10, 2023
    Assignee: NXP USA, Inc.
    Inventors: Rakesh Pandey, Mohit Arora, Jun Xie
  • Patent number: 11526396
    Abstract: The invention relates to an interconnection network for forward error correction encoders and decoders, including N input terminals, N output terminals, and M stages. Each stage includes switching elements having input pins and output pins. The input pins of the switching elements of the first stage are connected to the input terminals, and the output pins of the switching elements of the last stage are connected to the output terminals. The input and output pins of the switching elements of immediately successive stages are connected in a hardwired fashion so as to form a plurality of interconnection sub-networks for routing respective input values from respective output pins of the switching elements of the first stage to respective input pins of the switching elements of the last stage.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: December 13, 2022
    Assignee: Thales Alenia Space Italia S.p.A. Con Unico Socio
    Inventors: Domenico Giancristofaro, Massimo Fonte
  • Patent number: 11522561
    Abstract: A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to constitute Low Density Parity Check (LDPC) information bits including the outer-encoded bits and zero bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the LDPC information bits are divided into a plurality of bit groups, and wherein the zero padder pads zero bits to at least some of the plurality of bit groups, each of which is formed of a same number of bits, to constitute the LDPC information bits based on a predetermined shortening pattern which provides that the some of the plurality of bit groups are not sequentially disposed in the LDPC information bits.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: December 6, 2022
    Inventors: Kyung-Joong Kim, Se-ho Myung, Hong-sil Jeong
  • Patent number: 11520563
    Abstract: Disclosed are an apparatus and method for transforming a matrix, and a data processing system. The apparatus may include: a first shift unit, configured to receive matrix data and perform first cyclic shift on the matrix data to generate first data; a cache unit, configured to write each row of data into the cache unit in the first data thereto in an order different from the order of respective data in the row of data to store the first data as second data; and a second shift unit, configured to read the second data from the cache unit and perform second cyclic shift on the second data to generate transformed matrix data.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 6, 2022
    Inventor: Xiaozhang Gong
  • Patent number: 11515891
    Abstract: A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: November 29, 2022
    Assignee: Intel Corporation
    Inventors: Santhosh K. Vanaparthy, Ravi H. Motwani
  • Patent number: 11515895
    Abstract: The present disclosure discloses a new coding scheme, which is constructed by superimposing together a pair of basic codes in a twisted manner. A SCL decoding algorithm is proposed for the TPST codes, which may be early terminated by a preset threshold on the empirical divergence functions (EDF) to trade off performance with decoding complexity. The SCL decoding of TPST is based on the efficient list decoding of the basic codes, where the correct candidate codeword in the decoding list is distinguished by employing a typicality-based statistical learning aided decoding algorithm. Lower bounds for the two layers of TPST are derived, which may be used to predict the decoding performance and to show the near-ML performance of the proposed SCL decoding algorithm. The construction of TPST codes may be generalised by allowing different basic codes for the two layers.
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: November 29, 2022
    Inventors: Xiao Ma, Suihua Cai
  • Patent number: 11513740
    Abstract: A hybrid memory system provides rapid, persistent byte-addressable and block-addressable memory access to a host computer system by providing direct access to a both a volatile byte-addressable memory and a volatile block-addressable memory via the same parallel memory interface. The hybrid memory system also has at least a non-volatile block-addressable memory that allows the system to persist data even through a power-loss state. The hybrid memory system can copy and move data between any of the memories using local memory controllers to free up host system resources for other tasks.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 29, 2022
    Inventors: Mike Hossein Amidi, Fariborz Frankie Roohparvar
  • Patent number: 11515896
    Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: November 29, 2022
    Inventors: Yasuyuki Imaizumi, Satoshi Shoji, Mitsunori Tadokoro, Takashi Ishiguro, Yifan Tang
  • Patent number: 11507875
    Abstract: A quantum device includes a syndrome measurement circuit that implements an correction code using a plurality of Majorana qubit islands. The syndrome measurement circuit is adapted to effect a syndrome measurement by performing a sequence of measurement-only operations, where each one of the measurement-only operations involves at most two of the Majorana qubit islands.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 22, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Roman Bela Bauer, Parsa Bonderson, Alan D Tran
  • Patent number: 11501843
    Abstract: A storage device is provided which shares a host memory with a host. The storage device includes an interface that exchanges data with the host and implements a protocol to use a partial area of the host memory as a buffer of the storage device. A storage controller of the storage device monitors deterioration information of a first area of the buffer and transmits a corruption prediction notification associated with the first area to the host based on a result of the monitoring.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: November 15, 2022
    Inventors: Dong-Ryoul Lee, Hyun Ju Yi, Jaeho Sim, Kicheol Eom, Hyotaek Leem
  • Patent number: 11487431
    Abstract: In write processing of a data set group to be written to be one or more data sets to be written, a storage system performs encoding processing including processing for generating a data model showing regularity of the data set group to be written and having one or more input values as an input and the data set group as an output. In the write processing, the storage system writes the data model generated in the encoding processing and associated with a key of the data set group to be written.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: November 1, 2022
    Assignee: HITACHI, LTD.
    Inventors: Hiroaki Akutsu, Akira Yamamoto
  • Patent number: 11487619
    Abstract: A first node group including at least three nodes is predefined in a distributed storage system. Each node of the first node group is configured to send data blocks stored in storage devices managed by the node to other nodes belonging to the first node group. A first node is configured to receive data blocks from two or more other nodes in the first node group. The first node is configured to create a redundant code using a combination of data blocks received from the two or more other nodes and store the created redundant code to a storage device different from storage devices holding the data blocks used to create the redundant code. Combinations of data blocks used to create at least two redundant codes in redundant codes created by the first node are different in combination of logical addresses of constituent data blocks.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: November 1, 2022
    Assignee: Hitachi, Ltd.
    Inventors: Hiroaki Akutsu, Shunji Kawamura, Kota Yasunaga, Takahiro Yamamoto, Atsushi Kawamura
  • Patent number: 11469777
    Abstract: The present disclosure provides a method for optimizing a protograph-based LDPC code over an underwater acoustic (UAW) channel. The traditional protograph-based LDPC code over an UAW channel does not consider performance in an error floor region. The method first determines parameters such as a protograph-based LDPC code length, a basic protograph, a target decoding threshold, a threshold adjustment factor, and an ACE check parameter. The protograph is optimized, and the method constructs a parity check matrix by using a UAW channel-based PEG/ACE hybrid algorithm, performs ACE check on the parity check matrix, and calculates a decoding threshold for the matrix passing the check. If the decoding threshold is within a range of an iterative decoding threshold, the parity check matrix is a final optimized matrix. Otherwise, the method continues to optimize the protograph until a parity check matrix passing the check is obtained.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: October 11, 2022
    Assignee: Zhejiang University
    Inventors: Lei Xie, Huifang Chen, Hongda Duan
  • Patent number: 11455289
    Abstract: A method for data storage, in a system that includes multiple servers, multiple multi-queue storage devices and at least one storage controller that communicate over a network, includes receiving in a server, from an application running on the server, a request to access data belonging to one or more stripes. The stripes are stored on the storage devices and are shared with one or more other servers. In response to the request, the following are performed at least partially in parallel: (i) requesting one or more global locks that prevent the other servers from accessing the stripes, and (ii) reading at least part of the stripes from the storage devices speculatively, irrespective of whether the global locks are granted. Execution of the request is completed upon verifying that the speculatively-read data is valid.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: September 27, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Alex Friedman, Sergei Dyshel, Ofir Dahan, Alex Liakhovetsky
  • Patent number: 11451246
    Abstract: An FEC codec module is provided. Code elements, i.e., code words of forward error correction code, are added to the data code stream of each transmission link through the codec module, so that accurate error determination and automatic error correction may be realized at the receiving end. The interleaving process is performed on multi-link data to prevent the occurrence of continuous burst errors in the data link in a transmission process, and the error correction capability of FEC is utilized to improve the data transmission efficiency and anti-interference ability of the system.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: September 20, 2022
    Inventors: Xuansheng Zhu, Shenghui Bao, Hui Bian, Sai Gao, Xinrun Xing
  • Patent number: 11438099
    Abstract: This application discloses an information processing method. A communication device obtains an input sequence. The input sequence has a quantity B of bits. The communication devices transforms the input sequence into one or more code blocks. The communication device encodes each of the code blocks, to obtain one or more encoded code blocks. Each of the code blocks has a code block length less than or equal to a maximum code block length. Each of the code blocks includes a segment of the input sequence, one or more cyclic redundancy check (CRC) bits corresponding to the segment of the input sequence, and one or more filler bits. The encoded code blocks can meet various channel coding requirements.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: September 6, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Chen Zheng, Liang Ma, Jie Xiong, Xin Zeng, Xiaojian Liu, Yuejun Wei
  • Patent number: 11431443
    Abstract: A method of operating a user equipment in a radio access network is disclosed. The method includes transmitting acknowledgment signaling based on a codebook, the codebook associating a bit pattern having comprising one or more subpatterns with the acknowledgment signaling. Each subpattern representing acknowledgment information according to a reporting type, in which the codebook groups subpatterns based on their reporting type.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: August 30, 2022
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Robert Baldemair, Mattias Andersson, Erik Dahlman, Stefan Parkvall