Patents Examined by Joseph D. Torres
  • Patent number: 11991034
    Abstract: A first wireless communication device may encode real samples of data to obtain encoded data based at least in part on adding one or more time domain complex samples to the real samples of the data. A function of the one or more time domain complex samples may be a known value, and the function may be a sum of exponentials of the one or more time domain complex samples. The first wireless communication device may transmit, to a second wireless communication device, the encoded data.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: May 21, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Ori Shental, Meilong Jiang, Ashwin Sampath, Ahmed Bedewy
  • Patent number: 11990921
    Abstract: Devices, systems and methods for list decoding of polarization-adjusted convolutional (PAC) codes are described. One example method for improving error correction in a decoder for data in a communication channel includes receiving a noisy codeword, the codeword having been generated using a polarization-adjusted convolutional (PAC) code and provided to the communication channel prior to reception by the decoder, and performing PAC list decoding on the noisy codeword, wherein an encoding operation of the PAC code comprises a convolutional precoding operation that generates one or more dynamically frozen bits, and wherein the PAC list decoding comprises extending, based on the one or more dynamically frozen bits, at least two paths of a plurality of paths in the PAC list decoding differently and independently.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: May 21, 2024
    Assignee: The Regents of the University of California
    Inventors: Hanwen Yao, Arman Fazeli Chaghooshi, Alexander Vardy
  • Patent number: 11966303
    Abstract: Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: April 23, 2024
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Robert Mason, Scott A. Stoller, Pitamber Shukla, Kenneth W. Marr, Chi Ming Chu, Hossein Afkhami
  • Patent number: 11966283
    Abstract: An exemplary computing device includes a plurality of circuits and/or a plurality of in-situ monitors configured to generate outputs that indicate one or more operating conditions of the circuits. The computing device also includes a system management unit configured to detect a potentially faulty voltage-to-frequency ratio implemented by one of the circuits based at least in part on one or more of the outputs. The system management unit is also configured to modify the potentially faulty voltage-to-frequency ratio based at least in part on one or more of the outputs. Various other devices, systems, and methods are also disclosed.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: April 23, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Divya Madapusi Srinivas Prasad, Sudhanva Gurumurthi, Yasuko Eckert, Jeffrey Richard Rearick, Sankaranarayanan Gurumurthy, Amitabh Mehra, Shidhartha Das, Alex W. Schaefer, Vikram Ramachandra, Vilas Sridharan
  • Patent number: 11967970
    Abstract: A scheme for determining a flipping energy used in a bit-flipping decoder. The flipping energy is determined based on: a weight of at least one check node coupled to a column; a syndrome as a product of a noisy codeword and a parity check matrix; and a hard decision value of a previous iteration and a channel output value associated with the column.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: April 23, 2024
    Assignee: SK hynix Inc.
    Inventors: Fan Zhang, Meysam Asadi, Haobo Wang
  • Patent number: 11967971
    Abstract: Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose-Chaudhuri-Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose-Chaudhuri-Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: April 23, 2024
    Assignee: Innogrit Technologies Co., Ltd.
    Inventors: Chenrong Xiong, Jie Chen
  • Patent number: 11949766
    Abstract: An interface obtains basic page information from another interface. The basic page information includes N bits, the N bits include an FEC function indicator bit sequence including an FEC ability indicator bit and an FEC requested indicator bit. The interface determines, based on values of a plurality of bits in the N bits, an operation mode supported by the another interface. The FEC function indicator bit sequence includes a first FEC function indicator bit corresponding to m FEC abilities; or the FEC function indicator bit sequence includes a first FEC ability indicator bit corresponding to n FEC abilities, where both m and n are greater than or equal to 1. Because one FEC function indicator bit indicates more FEC abilities, N bits in a basic page can carry more information, so that a process of increasing auto-negotiation pages is slowed down, thereby avoiding impact on auto-negotiation efficiency.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: April 2, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xiang He, Jun Hu
  • Patent number: 11947422
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: April 2, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Kenichiro Yoshii, Shinichi Kanno
  • Patent number: 11949436
    Abstract: Disclosed is a method of wireless communication. The method is performed at a first wireless node. The method comprises: obtaining a sequence of bits to be encoded, selecting a puncturing pattern from a plurality of puncturing patterns, generating, based on the sequence of bits to be encoded, a sequence of parity bits in accordance with a binary linear block coding scheme, puncturing, based on the selected puncturing pattern, at least one of the sequence of bits to be encoded or the sequence of parity bits, generating a plurality of modulation symbols based on remaining bits in the sequence of bits to be encoded and based on remaining bits in the sequence of parity bits, and transmitting, to a second wireless node, the plurality of modulation symbols.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: April 2, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Hobin Kim, Hari Sankar, Jing Jiang, Wei Yang, Gabi Sarkis
  • Patent number: 11949510
    Abstract: Embodiments include methods performed by a copy engine of a computing device for generating a cyclic redundancy check (CRC) in a safety network, including copying a first dataset received from an interface bus to obtain a first dataset copy, copying a second dataset received from the interface bus to obtain a second dataset copy, generating, via a first stream-wise CRC engine in the hardware of the copy engine, a first CRC value for the first dataset copy and, in parallel, generating, via a second stream-wise CRC engine in the hardware of the copy engine, a second CRC value for the second dataset copy, transmitting, to a processor of the computing device, a first stream-wise CRC message including the first dataset copy and the first CRC value, and a second stream-wise CRC message including the second dataset copy and the second CRC value.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: April 2, 2024
    Assignee: QUALCOMM Incorporated
    Inventor: Sunitha Annam Vijayasingh Gnanaprakasam
  • Patent number: 11942172
    Abstract: A chip having a debug function includes functional circuitries, a selector circuitry, a data reconstruction circuitry, and a switching circuitry. Each functional circuitry includes a decoder circuit that stores a corresponding set of debug signals and outputs a corresponding debug signal in the corresponding set of debug signals to be a corresponding signal in first signals according to a corresponding address signal in address signals. The selector circuitry selects second signals from the first signals according to the address signals. The data reconstruction circuitry selects first data from the second signals according to split signals and outputs the same to be debug data. Each first data is partial data of a corresponding signal in the second signals. The switching circuitry determines whether to output the debug data or at least one output signal associated with the functional circuitries via output ports according to switching signals.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: March 26, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Pan-Ting Jiang, Zan Li
  • Patent number: 11943060
    Abstract: Methods and systems for managing an error correction mode at a first communications router. The first communication router transmits data packets to a second communications router and stores the first data packet in a local storage medium. When a delay inquiry message is received from the second communications router, the first communications router activates the error correction mode. When the error correction mode is activated, the first data packet is retransmitted to the second communications router and an error correction packet corresponding to the first data packet is also transmitted. When a back-to-normal message is received from the second communications router, the first communications router deactivates the error correction mode. The back-to-normal message indicates that the first communications router no longer needs to be in error correction mode.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: March 26, 2024
    Assignee: Pismo Labs Technology Limited
    Inventors: Patrick Ho Wai Sung, Kam Chiu Ng, Ho Ming Chan
  • Patent number: 11942964
    Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: March 26, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Shrinivas Kudekar, Thomas Joseph Richardson
  • Patent number: 11936400
    Abstract: The disclosure relates to a fifth generation (5G) or sixth generation (6G) communication system for supporting a higher data transmission rate. An encoding apparatus may obtain state-indicator information indicating a state of each of bits included in the polar code based on an index set of the bits, identify a weak-bit or a second weak-bit corresponding to a parity bit candidate position preset according to an interconnection within a parity-check (PC)-chain of the polar code and between PC-chains of the polar code as a parity bit, based on a number of weak-bits determined according to the state-indicator information and a number of bits to be used as parity bits, and obtain a polar code including the identified parity bit.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: March 19, 2024
    Assignees: Samsung Electronics Co., Ltd., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Kwonjong Lee, Seunghyun Lee, Sanghyo Kim, Minyoung Chung, Hyosang Ju, Jisang Park
  • Patent number: 11936401
    Abstract: A Polar code decoding method and apparatus, a storage medium, and a terminal are provided. The method includes: dividing a Polar code having a length of N into S groups of Polar codes, each group of the S groups of Polar codes being data extracted from the Polar code having the length of N according to a preset rule, and S being an integer power of 2; and performing joint decoding on calculation results of the S groups of Polar codes after performing a logarithm likelihood ratio (LLR) calculation on each group of the S groups of Polar codes.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: March 19, 2024
    Assignee: SANECHIPS TECHNOLOGY CO., LTD.
    Inventor: Guangming Shi
  • Patent number: 11936403
    Abstract: Systems and methods are provided for decoding data read from non-volatile storage devices. A method that may include decoding a first codeword read from a storage location of a non-volatile storage device using a first decoder without soft information, determining that the first decoder has failed to decode the first codeword, decoding the first codeword using a second decoder without soft information, determining that the second decoder has succeeded in decoding the first codeword, generating soft information associated with the storage location using decoding information generated by the second decoder and decoding a subsequent codeword from the storage location using the soft information associated with the storage location. The second decoder may be more powerful than the first decoder.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: March 19, 2024
    Assignee: Innogrit Technologies Co., Ltd.
    Inventors: Bo Fu, Jie Chen, Han Zhang, Zining Wu
  • Patent number: 11929764
    Abstract: For an encoder for use in a flash memory controller, partial parity blocks generated in the encoder are divided into two parts for further operations, wherein a number of partial parity block(s) of the first part generated earlier is less than a number of partial parity block(s) of the second part. The encoder can reduce the hardware required for the circulant convolution calculation in the encoder, and has high efficiency. In addition, by converting a parity-check matrix to generate an isomorphic matrix, some components in the encoder and the decoder can be further omitted, so as to further reduce the manufacturing cost.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: March 12, 2024
    Assignee: Silicon Motion, Inc.
    Inventor: Duen-Yih Teng
  • Patent number: 11923872
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: March 5, 2024
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11916574
    Abstract: A receiver includes an error correction module. A syndrome value, calculated based on received signals, may be used to enable the error correction module. The error correction module includes an error generator, a Nyquist error estimator, and a decoder. The decoder uses error estimation generated by the Nyquist error estimator to correct the decoded data. There are other embodiments as well.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: February 27, 2024
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Benjamin P. Smith, Jamal Riani
  • Patent number: 11916572
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: February 27, 2024
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur