Abstract: A checksum addition method includes obtaining a command and an address transmitted from a request source; reading data from the address according to the command; calculating a checksum to be added to the data; and transmitting the checksum and the data to the request source, wherein the calculating calculates the checksum in a data unit according to a type of the command.

Abstract: An electroforming process for a resistive memory of a memory device including a memory controller, an encoder computing an inversion-invariant linear error correction code, and a write device connected directly to the encoder. An electroforming device performing electroforming through write operations to such a resistive memory and to a method for checking a write operation.

Abstract: A method and apparatus for transmitting information through a topological quantum error correction system based on multi-space-time transformation including steps of initializing quantum information, detecting an error in quantum information transmission, correcting the error in quantum information transmission, and decoding the information in quantum information transmission. Information safety is improved and only a quantity of devices for generating quantum states needs to be increased. A stabilizer is used to analyze code symmetry, for error detection, measurement, and correction. Any information about an encoded qubit is not revealed during odd/even parity measurement, so that an encoding state of the encoded qubit remains unchanged. A double-layer convolutional neural network model in an adversarial network can find an error correction chain with a best effect.

Abstract: A method for testing a stacked integrated circuit device comprising a first die and a second die, the method comprising: sending from testing logic of the first die, first testing control signals to first testing apparatus on the first die; in response to the first testing control signals, the first testing apparatus running a first one or more tests for testing functional logic or memory of the first die; sending from the testing logic of the first die, second testing control signals to the second die via through silicon vias formed in a substrate of the first die; and in dependence upon the second testing control signals from the first die, running a second one or more tests for testing the stacked integrated circuit device.

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Abstract: Methods, systems, and devices for one or more acceleration engines for memory sub-system operations are described. An acceleration engine can perform one or more validation procedures on one or more codewords of a management unit. The acceleration engine can collect validation data for the management unit based on performing the validation procedures. The acceleration engine can aggregate the validation data into group validation data associated with a set of management units. The acceleration engine can transmit the group validation data to firmware of a memory sub-system or a host device.

Abstract: A method, of decoding error correction code of a memory device with dynamic bit error estimation, can include generating at least one metric corresponding to one or more syndromes associated with a code word, the code word comprising an error correction code of a memory device, decoding the code word by a first decoder integrated with the memory device, in response to a determination that the metric satisfies a threshold associated with the syndromes, the first decoder having a first execution property, and decoding the code word by a second decoder integrated with the memory device, in response to a determination that the metric does not satisfy the threshold associated with the syndromes, the second decoder having a second execution property distinct from the first execution property, or in response to a determination that the metric satisfies the threshold associated with the syndromes, and in response to a determination to perform further decoding.

Abstract: A syndrome calculation circuit includes a matrix product calculation circuit. The matrix product calculation circuit is configured to generate syndrome bits in a composite field by calculating a matrix product of input data bits and a first arithmetic matrix. The first arithmetic matrix is a matrix product of a basis conversion matrix for converting a data string from a Galois field to the composite field and a second arithmetic matrix, which is at least a part of a parity check matrix.

Abstract: Devices, systems and methods for list decoding of polarization-adjusted convolutional (PAC) codes are described. One example method for improving error correction in a decoder for data in a communication channel includes receiving a noisy codeword, the codeword having been generated using a polarization-adjusted convolutional (PAC) code and provided to the communication channel prior to reception by the decoder, and performing PAC list decoding on the noisy codeword, wherein an encoding operation of the PAC code comprises a convolutional precoding operation that generates one or more dynamically frozen bits, and wherein the PAC list decoding comprises extending, based on the one or more dynamically frozen bits, at least two paths of a plurality of paths in the PAC list decoding differently and independently.

Abstract: A first wireless communication device may encode real samples of data to obtain encoded data based at least in part on adding one or more time domain complex samples to the real samples of the data. A function of the one or more time domain complex samples may be a known value, and the function may be a sum of exponentials of the one or more time domain complex samples. The first wireless communication device may transmit, to a second wireless communication device, the encoded data.

Abstract: Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose-Chaudhuri-Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose-Chaudhuri-Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.

Abstract: An exemplary computing device includes a plurality of circuits and/or a plurality of in-situ monitors configured to generate outputs that indicate one or more operating conditions of the circuits. The computing device also includes a system management unit configured to detect a potentially faulty voltage-to-frequency ratio implemented by one of the circuits based at least in part on one or more of the outputs. The system management unit is also configured to modify the potentially faulty voltage-to-frequency ratio based at least in part on one or more of the outputs. Various other devices, systems, and methods are also disclosed.

Abstract: A scheme for determining a flipping energy used in a bit-flipping decoder. The flipping energy is determined based on: a weight of at least one check node coupled to a column; a syndrome as a product of a noisy codeword and a parity check matrix; and a hard decision value of a previous iteration and a channel output value associated with the column.

Abstract: Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.

Abstract: Disclosed is a method of wireless communication. The method is performed at a first wireless node. The method comprises: obtaining a sequence of bits to be encoded, selecting a puncturing pattern from a plurality of puncturing patterns, generating, based on the sequence of bits to be encoded, a sequence of parity bits in accordance with a binary linear block coding scheme, puncturing, based on the selected puncturing pattern, at least one of the sequence of bits to be encoded or the sequence of parity bits, generating a plurality of modulation symbols based on remaining bits in the sequence of bits to be encoded and based on remaining bits in the sequence of parity bits, and transmitting, to a second wireless node, the plurality of modulation symbols.

Abstract: Embodiments include methods performed by a copy engine of a computing device for generating a cyclic redundancy check (CRC) in a safety network, including copying a first dataset received from an interface bus to obtain a first dataset copy, copying a second dataset received from the interface bus to obtain a second dataset copy, generating, via a first stream-wise CRC engine in the hardware of the copy engine, a first CRC value for the first dataset copy and, in parallel, generating, via a second stream-wise CRC engine in the hardware of the copy engine, a second CRC value for the second dataset copy, transmitting, to a processor of the computing device, a first stream-wise CRC message including the first dataset copy and the first CRC value, and a second stream-wise CRC message including the second dataset copy and the second CRC value.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.

Abstract: An interface obtains basic page information from another interface. The basic page information includes N bits, the N bits include an FEC function indicator bit sequence including an FEC ability indicator bit and an FEC requested indicator bit. The interface determines, based on values of a plurality of bits in the N bits, an operation mode supported by the another interface. The FEC function indicator bit sequence includes a first FEC function indicator bit corresponding to m FEC abilities; or the FEC function indicator bit sequence includes a first FEC ability indicator bit corresponding to n FEC abilities, where both m and n are greater than or equal to 1. Because one FEC function indicator bit indicates more FEC abilities, N bits in a basic page can carry more information, so that a process of increasing auto-negotiation pages is slowed down, thereby avoiding impact on auto-negotiation efficiency.

Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.

Abstract: Methods and systems for managing an error correction mode at a first communications router. The first communication router transmits data packets to a second communications router and stores the first data packet in a local storage medium. When a delay inquiry message is received from the second communications router, the first communications router activates the error correction mode. When the error correction mode is activated, the first data packet is retransmitted to the second communications router and an error correction packet corresponding to the first data packet is also transmitted. When a back-to-normal message is received from the second communications router, the first communications router deactivates the error correction mode. The back-to-normal message indicates that the first communications router no longer needs to be in error correction mode.