Abstract: The present disclosure includes apparatuses, methods, and systems for error identification on executed code. An embodiment includes memory and circuitry configured to read data stored in a secure array of the memory, identify a different memory having an error correcting code (ECC) corresponding to the read data of the memory, execute an integrity check to compare the ECC to the read data of the memory; and take an action in response to the comparison of the read data of the memory and the ECC, wherein the comparison indicates that the ECC identified an error in the read data of the memory.

Abstract: This application discloses a method and an apparatus for processing information, a communications device, and a communications system. The communications device is configured to obtain a starting position of an output bit sequence in a coded block in a circular buffer, and determine the output bit sequence in the coded block based on a length of the output bit sequence and the starting position. A value of the starting position is one of {p0, p1, p2, . . . , pkmax?1}, where 0?pk<NCB, pk is an integer, k is an integer, 0?k<kmax, NCB is a size of the coded block, and kmax is an integer greater than or equal to 4.

Abstract: Apparatus and methods for recovery after an abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.

Abstract: Various embodiments are directed to Reed-Muller decoding systems and methods based on recursive projections and aggregations of cosets decoding, exploiting the self-similarity of RM codes, and extended with list-decoding procedures and with outer-code concatenations. Various embodiments are configured for decoding RM codes (and variants thereof) over binary input memoryless channels, such as by, for each received word of RM encoded data, projecting the received word onto each of a plurality of cosets of different subspaces to form thereby a respective plurality of projected words; recursively decoding each of the respective plurality of projected words to form a respective plurality of decoded projected words; and aggregating each of the respective decoded projected words to obtain thereby a decoding of the corresponding received word of RM encoded data.

Abstract: Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.

Abstract: High-throughput software-defined convolutional interleavers and de-interleavers are provided herein. In some examples, a method for generating convolutionally interleaved samples on a general purpose processor with cache is provided. Memory is represented as a three dimensional array, indexed by block number, row, and column. Input samples may be written to the cache according to an indexing scheme. Output samples may be generated every MN samples by reading out the samples from the cache in a transposed and vectorized order.

Abstract: Example systems, read channel circuits, data storage devices, and methods to provide signal correction based on soft information in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, and a signal correction circuit. The soft output detector passes detected data bits and corresponding soft information to the signal correction circuit. The signal correction circuit uses the soft information to determine a signal correction value, which is combined with input signal to return a corrected signal to the soft output detector for a next iteration. In some configurations, the signal correction value may compensate for DC offset, AC coupling poles, and/or signal asymmetries to reduce baseline wander in the read channel.

Abstract: A syndrome calculation circuit includes a matrix product calculation circuit. The matrix product calculation circuit is configured to generate syndrome bits in a composite field by calculating a matrix product of input data bits and a first arithmetic matrix. The first arithmetic matrix is a matrix product of a basis conversion matrix for converting a data string from a Galois field to the composite field and a second arithmetic matrix, which is at least a part of a parity check matrix.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: Memory units are accessed using address bits. The address bits used to access memory units can have various formats. The address bits to access successive locations that are to be sequentially accessed can have a reduced Hamming distance binary code format to reduce a quantity of toggling to switch from one set of address bits to another set of address bits.

Abstract: Systems and methods are provided for decoding data read from non-volatile storage devices. A method may comprise receiving a chunk of data read from a physical location of a non-volatile storage device and searching a memory for soft information associated with the physical location using a unique identifier associated with the physical location. The soft information may be generated from one or more previous decoding processes on previous data from the physical location. The method may further comprise retrieving the soft information identified by the unique identifier associated with the physical location from the memory, decoding the chunk of data with the soft information indicating reliability of bits in the chunk of data and updating the soft information with decoding information generated during the decoding.

Abstract: A parity interleaving apparatus and method for fixed length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

Abstract: In a reliable multi-cast, a concealment scheme may be applied to recover or conceal lost or otherwise corrupted packets of audio information for one channel based on the audio information of other channels in the reliable multi-cast. The concealment scheme may employ correction factors for channels derived from the channel relationships.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.

Abstract: Methods, systems, and apparatuses for stall mitigation in iterative decoders are described. A codeword is received from a memory device. The codeword is iteratively error corrected based on a first bit flipping criterion. A stall condition in the multiple error correction iterations is detected. In response to the detection, the codeword is error corrected based on a second bit flipping criterion that is different from the first bit flipping criterion.

Abstract: An operation method of a receiving node may include performing a decoding operation for calculating first and second output transform values corresponding to first and second unit output nodes in each of a plurality of operation units constituting the polar decoder, based on first and second input transform values corresponding to first and second unit input nodes, and the decoding operation may include setting initial values of first and second variables for calculating the first output transform value; performing an iterative loop operation for updating the first and second variables; and calculating the first output transform value based on values of the first and second variables updated until a time when the iterative loop operation is terminated, wherein the iterative loop operation is terminated without performing iterations in which the first and second variables are determined not to be updated among a plurality of iterations.

Abstract: An approach includes a method, product, and apparatus for dynamically removing sparse data on a pixel by pixel basis. In some embodiments, a machine learning processing job is received. The machine learning processing job is then executed on a pixel by pixel basis by selecting non-zero data values for input into a systolic array, wherein sparse data is not selected for input into the systolic array. Subsequently, a message is generated that provides an indication of whether the execution completed successfully. In some embodiments, the machine learning processing job comprises at least a plurality of multiply and accumulate operations. In some embodiments, at least one data value equal to zero for the machine learning processing job is not input into a systolic array. In some embodiments, a plurality of weights are input into a plurality of columns for each cycle.

Abstract: An error rate measuring apparatus includes: an operation unit that sets a codeword length, an FEC symbol length, and an FEC symbol error threshold; error counting unit for counting FEC symbol error and an uncorrectable codeword; a display unit that performs display by setting one zone of a display area as one FEC symbol length, matching a zone length of a horizontal axis of the display area with one codeword length, and performing line feed in codeword length units according to presence or absence of the FEC symbol error in FEC symbol length units based on a counting result; search unit for searching for the uncorrectable codeword starting from the cursor on the identification display; and display control unit for performing display control of the cursor at a position of a head error of the searched uncorrectable codeword.

Abstract: A one-shot state transition decoder receives a codeword having N-bits. The decoder reads a first D-bits of the codeword to determine a stitching location d within the codeword. The stitching location identifies a start bit of unencoded data in the codeword. The codeword is decoded into an output buffer for user data of L bits, where N>L. Parameters of the decoder are set before the decoding, including setting a length of the codeword to N?L+d and a number of expected decoded bits to d. The decoding including decoding the d bits based on a set of state transition probabilities and copying decoded bits into the output buffer, the unencoded data being copied to the end of the output buffer.

Abstract: The present invention discloses methods and systems for managing an error correction mode at a first communications router. The first communication router transmits data packets to a second communications router and stores the first data packet in a local storage medium. When a delay inquiry message is received from the second communications router, the first communications router activates the error correction mode. When the error correction mode is activated, the first data packet is retransmitted to the second communications router and an error correction packet corresponding to the first data packet is also transmitted. When a back-to-normal message is received from the second communications router, the first communications router deactivates the error correction mode. The back-to-normal message indicates that the first communications router no longer needs to be in error correction mode.