Abstract: The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.

Abstract: An alpha radiation immune integrated circuit memory cell has a pair of secondary transistors connected to cross-couple the primary transistors to form a flow, secondary storage node. The secondary transistors are biased to a standby current that, in combination with the parasitic capacitances in the new cell, establishes a time constant sufficient to maintain the state of the secondary nodes during an alpha hit on the primary nodes, so that alpha immunity is achieved without added capacitance. A write boost circuit increases the current in the secondary transistors during a write operation. A memory array is formed of rows of such cells with all of the secondary emitters of each row coupled to a common emitter standby current source.

Abstract: A semiconductor device has a well region formed in the surface of a substrate, and has semiconductor elements such as MOSFETs and bipolar transistors formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.

Abstract: In a gate turn-off power semiconductor component in the form of a field-controlled thyristor (FCTh) with (14) separated from each other by trenches (10), means of control which make possible a constricton of the current-carrying channel over the entire depth of the cathode finger (14) and at the same time do not increase or do not substantially increase the ON resistance of the component are additionally provided in the region of the trench walls (9).In an exemplary embodiment, a p-doped wall layers (4), which have a reduced doping concentration compared with the gate regions (8) on the trench floors are introduced into the trench walls (9) as means.

Abstract: For improvement of signal-to-noise ratio and elimination of soft errors, there is disclosed a semiconductor memory device including a plurality of memory cells, each memory cell comprising a storage capacitor having a first electrode formed in side and bottom wall portions defining a primary cavity opened at a major surface of a semiconductor substrate, a thin dielectric film covering the side and bottom wall portions and substantially dictated by the configuration of the side and bottom wall portions to define a secondary cavity, and a second electrode filling the secondary cavity and projecting from the major surface of the semiconductor substrate, a thick insulating layer covering the major surface of the semiconductor substrate and formed therein an opening substantially aligned with the secondary cavity to allow the second electrode to extend over the surface of the thick insulating layer, and a switching transistor provided on the thick insulating layer and having source/ drain regions separated from ea

Abstract: An improved insulated gate semiconductor device is provided with an extra short grid region of one type conductivity disposed proximate the PN junction between the first and second regions of the device. The extra short grid region provides an alternate path for one type conductivity carriers to inhibit forward biasing of the PN junction between the first and second electrodes. In addition, the grid allows opposite type conductivity carriers to flow therethrough. A portion of the grid is spaced and separated from the first region. Accordingly, a device fabricated in accordance with the present invention is less susceptible to latching and exhibits a higher voltage latching threshold.