Abstract: This invention relates to a memory device internally employing an active period control signal for controlling an active period and an inactive period for internal operation. The memory device comprises a plurality of word lines and bit lines; memory cells provided at intersections thereof; a booster circuit, having an output terminal, for outputting to the output terminal a higher voltage than a power source voltage; and word drivers, connected to each of the word lines, for connecting the output terminal of the booster circuit to a corresponding word line in response to a word selection signals provided during the active period. The memory device also comprises a boosting control signal generation circuit supplying the booster circuit with a boosting control signal to continue a boosting operation of the booster circuit longer than the active period in response to the active period control signal.

Abstract: The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.

Abstract: A synchronous semiconductor memory device has an M-bit I/O configuration memory device mode and an M.times.2.sup.k -bit I/O configuration memory device mode. In the former mode, n bits whose transition frequencies are smaller are selected from an m-bit internal address and are used to access a memory section, while the other k (=m-n) bits whose transition frequencies are larger are selected from the m-bit internal address to select one of 2.sup.k groups of internal data lines of the memory section and connect them to some of data input/output pins. In the latter mode, n bits whose transition frequencies are larger are selected from the m-bit internal address and are used to access the memory section, while the 2.sup.k groups of the data lines are connected to all the data input/output pins.

Abstract: In a virtual-ground flash electrically programmable read-only-memory (EPROM), the pitch in the X direction of the floating gates, which are formed over a portion of vertically-adjacent field oxide regions, is reduced by forming the floating gates over continuous strips of vertically-adjacent field oxide. The strips of field oxide are formed in a layer of polysilicon which is formed over a layer of tunnel oxide which, in turn, is formed over the substrate.

Abstract: A method for programming a memory cell is disclosed. The state of the memory cell is determined by the presence or absence of a spacer short. A memory cell has a floating gate, a control gate and an insulating layer separating the floating gate and the control gate. Spacers are deposited on the sides of the control gate and the insulating layer. When the cell is selected to be programmed in the "off" or non-conductive state, the spacers are in contact only with the control gate and the insulating layer. When the cell is selected to be programmed in the "on" or conductive state, the spacers are in contact with the control gate, the insulating layer, and the floating gate, thereby creating a spacer short.

Abstract: The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.

Abstract: In this semiconductor integrated circuit device, an internal power supply circuit and an external terminal are connected to each other via a switch circuit having an n channel MOS transistor and a p channel MOS transistor connected in series. While a control signal is input to a gate of the n channel MOS transistor constituting the switch circuit, a control signal inverted by an inverter is input to a gate of the p channel MOS transistor. Thus, both transistors are simultaneously turned on/off by those control signals. When an output voltage of the internal power supply circuit is monitored from the external terminal or when an internal circuit of a semiconductor integrated circuit is driven by a voltage applied to the external terminal, even if a potential of the external terminal overshoots to positive or negative values, the transmission of the potential to the internal circuit is cut off by the n channel MOS transistor or p channel MOS transistor.

Abstract: A programmable EEPROM cell structure consisting in a split-gate structure in series with a coupling capacitor between the floating gate and an additional program gate in order to provide enhanced injection efficiency. The electron injection is controlled by a control gate at the source side. The area of the coupling capacitor is selected with a substantial coupling factor to a high voltage onto the floating gate during programming so as to produce hot-electron injection at the split point in the channel region between the control gate and the floating gate. Submicrosecond programming at a 5 V drain voltage can thereby be achieved.

Abstract: A programmable EEPROM cell structure consisting in a split-gate structure in series with a coupling capacitor between the floating gate and an additional program gate in order to provide enhanced injection efficiency. The electron injection is controlled by a control gate at the source side. The area of the coupling capacitor is selected with a substantial coupling factor to a high voltage onto the floating gate during programming so as to produce hot-electron injection at the split point in the channel region between the control gate and the floating gate. Submicrosecond programming at a 5 V drain voltage can thereby be achieved.

Abstract: A processor (10) comprises a plurality of processing elements each having an input register (11), first memory bank (12), first sense amplifier (40), ALU (13), output register (16), second memory bank (15) and second sense amplifier (42). The first sense amplifier (40) is shared between the input register (11) and first memory bank (12). The second sense amplifier (42) is shared between the output register (16) and second memory bank (15). The sense amplifier (40,42) may be paused to prevent voltage spikes during a read/write operation, or to wait until a calculation is completed.

Abstract: Distributed buffering memory device (10) is provided which includes memory circuitry (12) located therein and independent buffering circuitry (16). Device (10) can be used in an array of devices where buffering circuitry (16) is employed to buffer the signals necessary for the array. Each independent buffer is employed to buffer a signal and supply that signal to a bank unique input bus which is used to drive the inputs of the array.

Abstract: In a memory card designed to count down a number of units by successive programming of non-volatile, electrically erasable and electrically programmable memory cells, the memory is organized into N rows of P cells, the weight of the cells of one row in the account being P times the weight of the next-ranking row. The countdown procedure is recurrent and consists in making a search, in scanning the memory according to the rising order of weights, of an erased cell, programming this cell and an erased cell and then erasing the entire row having an immediately lower rank unless the erased cell is located in the first row, and in recommencing this recurrent procedure until an erased cell is found in the first line. The auxiliary cell enables the detection of an abnormal interruption of the recurrent procedure and the restoring of the exact account of the memory which could have been distorted by this abnormal interruption.

Abstract: An integrated circuit includes primary circuit elements selectable by n address bits. A master storage device is programmable to indicate that at least one primary circuit element is being replaced. Redundant circuit elements each include a non-precharging matching circuit, which includes sub-match circuits. The sub-match circuits include two state storage devices corresponding to one of the possible binary values of at least one of the n address bits and activate a sub-match signal when the binary value of the at least one of the n address bits corresponds to one of the two state storage devices in a first state if the master storage device is programmed. A match circuit activates a match signal in response to all sub-match signals being active to disable a primary circuit element from being selected by a corresponding binary value of the n address bits and to enable the redundant circuit element to be selected by the corresponding binary value of the n address bits.

Abstract: In a dynamic random access memory device including a plurality of word lines, a plurality of bit lines, and a plurality of dynamic memory cells connected to the word lines and the bit lines, a switching circuit is provided between one pair of the bit lines and one sense amplifier, and a switching amplifier is provided between one pair of the bit lines and a read amplifier. Before the connection of the sense amplifier by the switching circuit to the pair of the bit lines, the read amplifier is connected by the switching amplifier to the pair of the bit lines.

Abstract: An improved one-transistor flash EEPROM cell structure and a method for making the same is provided so that the effective channel length dimension is independent of the critical dimensions of the stacked gate structure. The cell structure (210) includes an n.sup.- buried channel/junction region (216) which is implanted in a substrate (212) before formation of a tunnel oxide (226) and a stacked gate structure (234). After the formation of the stacked gate structure, a p-type drain region (222) is implanted with a large tilt angle in the substrate. Thereafter, n.sup.+ source and n.sup.+ drain regions (218, 224) are implanted in the substrate so as to be self-aligned to the stacked gate structure. The cell structure of the present invention facilitates scalability to small size and is useful in high density application.

Abstract: In a semiconductor memory device and a method for using the semiconductor memory device, the semiconductor memory device includes a plurality of memory cells series-connected to each other, and each formed by a P-channel transistor in which a control gate electrode is stacked via an insulating film on a floating gate electrode. One end of the plural memory cells series-connected to each other is connected to one of a source and a drain of a first selecting transistor. The other of the source and the drain of the first selecting transistor are connected to a bit line. The other end of the plural memory cells series-connected to each other is connected to one of a source and a drain of a second selecting transistor. The other of the source and the drain of the second selecting transistor is connected to a power source line.

Abstract: Disclosed is a semiconductor memory device carrying out reading and writing operations of data, comprising memory means consisting of a plurality of memory cells for storing data; test signal generation means for generating a test signal upon a test being carried out; at least one first buffer for receiving an external address bit and generating inverting and noninverting address bits; at least one second address buffer for selectively receiving said external address bit in response to said test signal from said test signal generation means and generating said inverting and noninverting address bits or the signals of the same logic value through two output terminals thereof; decoding means for receiving output signals from said first and second address buffers and selecting one or plural corresponding memory cells of said memory means; and voltage level compensation means for compensating a voltage level applied to each of words lines of said memory cells selected by said decoding means in accordance with sai

Abstract: A power-up circuit in a computer system drives a memory device such as a dynamic random access memory (DRAM) to an initial condition after the computer system is turned on or reset. The power-up circuit also advantageously drives the memory device into the initial condition upon detecting a transient such as a negative glitch in a supply voltage being provided to the memory device. The power-up circuit includes a voltage level detector which causes a power-up signal to be provided to the memory device upon detecting that the supply voltage is less than a threshold voltage of the memory device which is necessary for the memory device to operate in an operational state.

Abstract: A low voltage flash EEPROM X-Cell includes an array of memory cell transistors (24) that constitute asymmetric floating gate memory cells wherein programming is achieved on only one side of the memory cells (24). The programming side of each of the memory cells (24) is connected to one of a plurality of Column Lines (28) at nodes (30). Each node (30) shares the programming side of two of the memory cells (24) and the non-programming side of two of the memory cells (24). The control gates of each of the memory cells (24) are connected to Word Lines (26) associated with rows of the array. To Flash Write all of the memory cells (24), the Column Lines (38) are connected to a negative medium voltage and the row lines (26) are connected to a positive medium voltage.

Abstract: The present invention is intended to operate a semiconductor device at high speed with low voltage. A circuit configuration is used in which the transfer impedance between a common I/O line and a data line is changed depending on whether information is to be read or written. A current/voltage converter is provided which includes a MISFET different in conduction type to a select MISFET. Thus, the speed of reading information is increased. An intermediate voltage generator having high driving capability is provided. Thus, the circuit has sufficient driving capability for an LSI having large load capacitance. A voltage converter is provided which converts a data line supply voltage or word line supply voltage to a higher voltage. Therefore, stabilized signal transmission is ensured.