Abstract: A semiconductor memory device, includes a memory cell array, a row decoder connected to the memory cell array by a plurality of word lines for selecting a word line in response to a first address signal supplied thereto, a column decoder connected to the memory cell array by a plurality of bit lines for selecting a bit line in response to a second address signal supplied thereto, and a data discrimination unit connected to the column decoder by a common data bus for producing an output data signal indicative of the data stored in the addressed memory cell. The column decoder includes a plurality of sense amplifiers each connected to a corresponding bit line for selecting an addressed bit line. The plurality of sense amplifiers are connected to a common data bus for carrying data stored in the addressed memory cell. A plurality of switching devices are provided in correspondence to the plurality of sense amplifiers for selectively transferring the data detected by the sense amplifier to the common data bus.

Abstract: A semiconductor device includes memory cells each of which include a plurality of groups of an anti-fuse and a transistor connected in series; a capacitor including first and second electrodes, with the first electrode connected to a bit line of the memory cell; a first switch connected between the bit line and a power source; a second switch connected between the power source and the second electrode of the capacitor; and a third switch connected between the second electrode of the capacitor and a ground. A specific memory cell is selected out of the memory cells, and a superposed supply voltage is applied through the capacitor to the anti-fuse of the specific memory by turning on and/or off the first through third switches, so that a storage of information in the memory cell can be performed.

Abstract: A dynamic random access memory device for storing 2-bit information, including a memory cell having two access transistors and one capacitor, wherein one of the access transistors is composed of a thin film transistor and disposed above the other access transistor which is formed in a substrate; and the capacitor is sandwiched by the two access transistors.

Abstract: A method for initilizing redundant circuitry of a semiconductor memory device is disclosed. The method comprises sectioning the redundant circuitry and applying an initilizing pulse to each section of redundant circuitry at a different time during power up. Such a method is useful setting the redundant circuits in a dynamic random access memory device.

Abstract: The apparent voltage used to program an EEPROM cell is increased by applying a negative voltage to the memory control gate of the sense transistor in the cell. This method is applicable to devices in which the substrate is negatively biased.

Abstract: A dynamic random access memory device comprises memory cells arranged in rows and columns and storing data bits, respectively, bit line pairs respectively coupled to every two columns of the memory cells for propagating the data bits read out from the memory cells, word lines respectively coupled to the rows of the memory cells and allowing the data bits stored in one of the rows of the memory cells to be read out to the bit line pairs, sense amplifier circuits provided in association with the bit line pairs and selectively coupling the component bit lines to first and second sources of voltage level depending upon the logic level of the data bits, a pair of data signal lines coupled to an output data buffer circuit, a column selector unit coupled between the bit line pairs and the data signal lines and sequentially interconnecting the bit line pairs and the data signal lines in a static column mode of operation, and a precharging unit coupled to the data signal lines and having current paths from the first s

Abstract: A digital memory circuit for electronic applications. The circuit has at least one memory element connected in series with a load resistor. The digital memory circuit also includes a voltage supply and a data output terminal. The memory element in the digital memory circuit is in the form of a silicon dioxide film derived from a hydrogen silsesquioxane resin. The silicon dioxide film is characterized by a jV curve which includes both resistive and conductive regions for the memory element.

Abstract: A semiconductor memory device, in which based on a write and non-write states of a memory transistor, a signal corresponding to a page mode and a normal mode is generated, and a switch circuit activates all sense amplifiers corresponding to memory array blocks and transfers data read out of the memory array blocks to the sense amplifiers in the page mode and also activates one of the sense amplifiers and successively transfers the data read out of the memory cell array blocks to the one activated sense amplifier according to an address signal in the normal mode. A plurality of sense amplifiers are activated in the page mode and the minimum number of the sense amplifiers is activated in the normal mode to eliminate a waste of a consumption power.

Abstract: A write-in voltage source is incorporated in an electrically erasable read only memory device for supplying a write-in voltage level to memory circuits of a redundant unit as well as a data storage, and comprises a first control circuit responsive to a first instruction signal indicative of a power voltage level or a write-in voltage level and producing first and second control signals complementary to each other, a second control circuit responsive to a second instruction signal indicative of a ground voltage level and producing third and fourth control signals complementary to each other, a first level-shifting circuit responsive to the first to third control signals and producing one of the write-in voltage level, the power voltage level and the ground voltage level, and a second level-shifting circuit responsive to the first, second, and fourth control signals and producing one of the write-in voltage level, the power voltage level and the ground voltage level so that the first and second level-shifting c

Abstract: A semiconductor memory device includes a plurality of memory cells arranged along a word line. Each memory cell is constituted by a flip-flop formed by a pair of driver transistors of a first conductivity channel and a pair of load transistors of a second conductivity channel. The load transistors have an active layer formed by a semiconductor thin film.A power line connected to the load transistors includes a first metal layer that extends in a direction parallel to the word line and connections, arranged at intervals along the word line, between the first metal layer and the semiconductor thin film.A ground line is connected to the driver transistors and includes a second metal layer that extends in a direction parallel to the word line and a connecting portion that is connected to the second metal layer and extends in a direction perpendicular to the word line.

Abstract: A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.

Abstract: A byte-wide memory has a plurality of redundant columns. Each redundant column is capable of being mapped to any one of a plurality of input buffers and output buffers in place of a defective column. Fuse match logic circuits store the addresses of defective columns. I/O fuse decoder circuits are coupled to the fuse match logic circuits and store information identifying the input and output buffers associated with each defective column. The redundant columns are selected in response to a portion of the column address signals which select nonredundant columns. When a received column address matches a stored column address, the redundant column selected by the portion of column address signals is mapped to the input and output buffer associated with the defective column in place of the defective column.

Abstract: A 16 megabit dynamic random access memory device is active with an internal power voltage lower than an external power voltage for preventing extremely thin gate oxide films of the component field effect transistors from damage, a field effect transistor is coupled between an input terminal applied with an external signal as high as the external power voltage and an input logic gate for producing an internal signal as low as the internal power voltage, and the field effect transistor is supplied at the gate electrode with the internal power voltage so that the external signal steps down before reaching the input logic gate.

Abstract: A plurality of memory cell transistors having floating gates are disposed in a matrix in the direction of row and column to form a memory cell array. The memory cell array is divided into a plurality of sectors for every predetermined row. In each sector, sector selecting transistors and sub bit lines are provided, so that erasing and programming can be made for each sector. Therefore, total erasing for sector becomes possible, and since no voltage is applied to sub bit lines and word lines of non-selected sectors, the number of operations of preventing writing into non-selected memory cells is as many as the word lines included in one sector.

Abstract: A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines. Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines. Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers. More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.

Abstract: An integrated semiconductor circuit includes word lines and bit lines. A memory region has at least one memory cell field with memory cells addressable through the word lines and the bit lines, and a number of evaluator circuits corresponding to the number of the bit lines. Each of the evaluator circuits is connected with one of the bit lines and divides the one bit line into two at least approximately identical bit line halves. Logic units of a block perform digital processing of data read-out of the memory region through the bit lines and evaluated. Each of the logic units is connected to the two bit line halves of one of the bit lines. Various operating modes of the block of logic units are selected with mode select signals.

Abstract: Methods and apparatus are provided for using a partially functional memory device with extra fail bits to create a fully functional monolithic device. The concept may be expanded for use in waferscale integration. The concept may also be used to create a fully functional memory board using partially functional memory chips. To accomplish this, a distinct fail bit array is added to each memory chip and the defective bits in the main chip are replaced by bits in the fail bit array using a programmable element, such as a programmable logic array (PLA). The PLA generates fail bit access addresses to locations in the fail bit memory that replace the defective bits in the main array. Thus, the external address is simultaneously applied to both the main array and to the PLA. If there is a match between the external address and an internal location in the PLA, the PLA outputs a flag and a fail bit address which are used to disable the main array access and to enable access to the fail bit memory.

Abstract: A decoder for a memory redundancy scheme is disclosed which allows replacement of a number of memory cell locations in connection with the state of a plurality of fuses.

Abstract: An I/O circuit including first and second I/O pads, a fuse connected between the first pad and a RAM write enable line, and a diode-connected transistor connected between the RAM write enable line and second pad. Data is written to the RAM by applying a voltage potential to the pads after which the fuse is blown by increasing the potential difference. Other forms of the invention include a resistor connected between the RAM write enable line and ground, and I/O lines connected between the pads, respectively, and a logic circuit.

Abstract: A semiconductor memory device comprises a memory cell array (1) comprising a plurality of memory cells (MC) arranged in a matrix. A Y decoder (5) is responsive to an external address signal for outputting a selecting signal which simultaneously selects a plurality of columns in the memory cell array (1). The selecting signal is held by a latch transistor (LT). A selector (9b) sequentially applies input data to a plurality of columns simultaneously selected by the selecting signal held by the latch transistor (LT). During operation of the selector (9b), a binary counter (11) generates the subsequent internal column address signal, to which the Y decoder (5) is responsive for generating a selecting signal which simultaneously selects another plurality of columns in the memory cell array (1). As a result, the selecting operation in response to the subsequent selecting signal is performed immediately after operation of the selector (9b) is accomplished.