Abstract: The invention relates to a memory element in current circuit technology having a first, a second and a third transistor pair each with emitter coupled transistors. Each of the second and third transistor pairs is connected in the collector circuit of a respective one of the transistors of the first transistor pair. Connected in each of the pairwise coupled collector circuits of the transistors of the second and third transistor pairs are a first resistor, the collector-to-emitter path of a further transistor with an output signal terminal disposed on the collector side and a second resistor. The collector of one transistor of a fourth transistor pair connected as a current switch is connected with the base of one of the further transistors. The setting and resetting of the memory element is made possible by the fourth transistor pair without increasing the capacitive load on the signal path of the memory element.

Abstract: In an nonvolatile memory device, a transition circuit is provided between an output of a sense amplifier and an input of a write amplifier. In a write/read mode, data is transited from an input/output buffer via the transition circuit to an input of the write amplifier or from an output of the sense amplifier via the transition circuit to an input/output buffer. In a self-refresh mode, data from the output of the sense amplifier is fed back via the transition circuit to the input of the write amplifier.

Abstract: A circuit for producing a power up detection signal for use in, and being integrated onto the same semiconductor substrate as a dynamic memory device is disclosed. The circuit has a first node and a circuit to promote a low voltage on the first node when a voltage obtained from a supply voltage applied to the dynamic memory is below a predetermined level. It has a second node from which the power up detection signal can be removed. Included is a circuit to promote the obtained voltage on said second node when the obtained voltage is below the predetermined level, whereby the power up detection signal can be used to isolate the obtained voltage from the dynamic memory device. Included is a circuit to maintain a high voltage on the first node when the obtained voltage exceeds the predetermined level.

Abstract: An integrated EPROM device which can be manufactured using standard high-definition photolithographic techniques with unit cells of markedly reduced dimensions as compared to the minimum dimensions that can be achieved with the prior art, has field isolation structures between adjacent cells along rows of the array in the form of continuous isolation strips which extend for the whole column length of the array, thus avoiding the problems associated with photolithographic defining rectangular geometries. The electrical interconnection between the sources of the cells of each row is achieved by a special metal source "line" formed between two adjacent gate lines, using for the purpose a conformally deposited metal layer from which both the drain contacts and these source interconnection metal "lines" are created in a self-alignment way.

Abstract: A decimating memory includes a memory having addressable memory locations. The memory forms a plurality of registers, each of the registers including at least one addressable memory location. The plurality of registers form a forward shifting data section and a reverse shifting data section. A first decoder operates the registers in the forward shifting data section and all but a first of the registers in the reverse shifting data section as FIFO registers via read and write addressing of the addressable memory locations to input and output data samples. The read and write addressing of the addressable memory locations is offset with respect to one another to provide a decimation factor. A paintbrush decoder operates the first register in the reverse shifting data section as a LIFO register for reverse sequencing data samples within blocks of data samples received from the forward shifting data section. Each of the registers in the forward shifting and reverse shifting data sections provide an output.

Abstract: A semiconductor ROM includes a plurality of word lines disposed in parallel and has a plurality of units which each includes: a first main bit line and a second main bit line which cross the word lines; first, second, third, and fourth, sub-bit lines disposed substantially in parallel to the first and second main bit lines, and each of which has a first end and a second end; four memory cell columns, each including a plurality of memory cells connected in parallel between respective adjacent two of the sub-bit lines; and a plurality of bank selecting switches for selecting one of the four memory cell columns. First ends of the first sub-bit line and the third sub-bit line are connected to the first main bit line, and the second ends of the second sub-bit line and the fourth sub-bit line are connected to the second main bit line.

Abstract: A method for programming a programmable read only memory (PROM) is useful for a PROM which has a source, a drain and a control gate. A DC signal is placed on the control gate. For example, the DC signal has a voltage of approximately 5 volts. An AC signal is placed on the drain. The AC signal, for example, oscillates between approximately 0 volts and 5 volts and has a frequency of at least 100 Megahertz. As a result, charges tunnel through a tunnel oxide region to an floating gate, thus programming the PROM.

Abstract: A non-volatile semiconductor memory device has an erasure control circuit which, during erasure operation, is switched to a source of a memory cell having a floating gate. The erasure control circuit is constituted by a resistor element and a reference transistor having the same structure as that of the memory cell. One end of the resistor element is connected to a node which, during erasure operation, is electrically connected to the source of the memory cell. The reference transistor has a drain connected to the node, a gate connected to a constant-voltage source, and a source grounded. A floating gate/substrate insulating film of the memory cell and a floating gate/substrate insulating film of the reference transistor are formed simultaneously in the same fabrication step so that the thickness of these insulating films are substantially the same.

Abstract: An encoder or an information reading device detects a scale with a probe that is vibrated at a predetermined frequency and amplitude in a predetermined direction. The angular positional relationship between the direction of probe vibration and the scale is detected according to frequency spectrum information of a detection signal obtained by detecting the scale with the vibrating probe.

Abstract: A semiconductor integrated circuit includes a circuit block whose operation is controlled by a inverted control signal whose significant potential level is set at a ground potential, and a wiring for transmitting a control signal for controlling the operation of the circuit block. An inverting circuit provided near the circuit block inverts the control signal and then supplies the inverted signal to the circuit block via a wiring. The inverter includes a first capacitor connected between the power source terminal and a node which is set at a high potential level in the inverter circuit when the control signal is set at the non-significant potential level and a second capacitor connected between a ground potential terminal and a node which is set at a ground potential level when the control signal is set at the non-significant potential level.

Abstract: A dynamic RAM is provided with enhanced charge storage capacity by increasing the surface area between the two electrodes of the storage capacitor. The first electrode consists of a thick conductive layer whose vertical sidewalls provide the extra surface area for charge storage. The second electrode is used to partially planarize the surface topology. The first electrode can also be used as the gate of a sensing transistor in a signal amplifying cell, as well as in multiport and multistate dynamic RAM cells.

Abstract: An erasable and programmable ROM with an identification code includes an internal circuit operating as an EPROM, a code reading circuit having a code setting circuit for storing a predetermined identification code, an output circuit, and a switching circuit for transferring an output of an internal circuit to the output circuit. The switching circuit is turned on to transfer the output signal of the internal circuit to the output circuit directly, when information in the internal circuit is read out. On the other hand, the switching circuit is turned off to separate the output circuit from the internal circuit, when the identification code is read out from the code setting circuit.

Abstract: A DRAM according to the present invention comprises a memory cell array having memory cells constituted by one transfer gate transistor (10) and a capacitor (11), and a peripheral circuit having a MOS transistor (45a) with the LDD structure. At least the source/drain region (19) connected to the capacitor of the transfer gate transistor is formed of a low concentration impurity region (19a). The low concentration impurity region has an impurity concentration substantially equal to that of the low concentration source/drain region (31) of the LDD MOS transistor of the peripheral circuit. The low concentration/drain region of the transfer gate transistor is formed by masking the surface thereof at the time of the high concentration ion implantation step for high concentration source/drain formation of the MOS transistor of the peripheral circuit.

Abstract: In a nonvolatile semiconductor memory device, a high voltage is selectively exerted between a word line to which the control gates of nonvolatile semiconductor memory elements are coupled and a source line to which the sources of the nonvolatile semiconductor memory elements are coupled, whereby charges stored in the floating gates are extracted through the source line. In addition, the nonvolatile semiconductor memory elements to be erased are provided with a source potential having ramp-rate characteristics such that the sources are gradually raised from a low voltage to the high voltage. Thus, the erasure of a predetermined part of the memory array of the memory device becomes possible in accordance with the division of the source lines or that of the word lines, and an excessive intense electric field can be prevented from acting between the floating gates and the sources because a ramp rate is used for the erasing high voltage.

Abstract: A random access memory includes a memory array of storage cells arranged in addressable rows and columns. A serial register is coupled to the memory array and to a serial register address decoder. A serial counter generates and applies to the serial register address decoder a sequence of addresses starting with an initial tap address. In response to the initial tap address, a first data bit is read out of an addressed storage cell of the memory array and is applied to a first input of a multiplexer. The initial tap address either is passed to the serial register address decoder or is incremented and applied to the serial register addressed decoder for accessing a second data bit from the serial register to a multiplexer. The initial tap address is incremented before passage only if the least significant bit of the initial address is odd.

Abstract: A semiconductor memory device including:a data storage device having a plurality of memory cells each capable of storing a data and being selected by an address, first complementary data corresponding to the data in a selected memory cell being outputted to first complementary data lines;a first equalizer for short-circuiting and equalizing the first complementary data lines;an amplifier for receiving the first complementary data from the first complementary data lines, making large the difference between levels of the first complementary data, and outputting as second complementary data the levels to second complementary data lines;a second equalizer for short-circuiting and equalizing the second complementary data lines;a data latch circuit having latch units and switching means, the latch unit receiving and latching the second complementary data from the second complementary data lines and outputting as third complementary data the second complementary data to third complementary data lines, the switching

Abstract: A plurality of single transistor memory cells arrayed in columns with the memory cells within a column connected to one or the other of precharged first and second output lines. An input line connected to the gate of the single transistor causes the first output line to be pulled to a first voltage when the cell is programmed a "true" and to be pulled to a second voltage when the cell is programmed a "complement". A pair of cross-coupled transistors connected between the first and second output lines of a column cause the second output line to be maintained at the precharged voltage when programmed a "true" and causes the first output line to be maintained at a precharged voltage when programmed a "complement".

Abstract: An I/O circuit including first and second I/O pads, a fuse connected between the first pad and a RAM write enable line, and a diode-connected transistor connected between the RAM write enable line and second pad. Data is written to the RAM by applying a voltage potential to the pads after which the fuse is blown by increasing the potential difference. Other forms of the invention include a resistor connected between the RAM write enable line and ground, and I/O lines connected between the pads, respectively, and a logic circuit.

Abstract: In a semiconductor memory array, each cell includes a semiconductor switching element and a capacitor with a ferroelectric material layer. The ferroelectric material layer is sandwiched between opposing electrodes and exhibits a polarization varied in response to a voltage applied across the electrodes in such a manner that the direction of polarization is reversed if the voltage reaches a polarization reversal voltage. First electrodes of the capacitor elements are constituted by portions of semiconductor regions of the associated switching elements, while the second electrodes of the capacitor elements of the cells are constituted by a single common conductor layer. A first conductor is connected in common with the second main semiconductor regions of the switching elements of those cells which are on one column. A second conductor is connected in common with control electrodes of the switching elements of those cells which are on one row.

Abstract: A semiconductor memory device has an aligner for aligning data. The aligner is disposed in front of a sense amplifier to directly receive data from an internal bus of a memory. This arrangement greatly reduces the time period from a data read to an arithmetic operation.