Patents Examined by Joseph Lauture
  • Patent number: 10237558
    Abstract: An encoder includes processing circuitry, a block memory, and a frame memory. The processing circuitry defines at least one parameter for each of plural types of segment_ids, splits an image into blocks, assigns, to each of the blocks, segment_id according to a type of the block, among the plural types of segment_ids, and sequentially encodes the blocks. In encoding the blocks, the processing circuitry identifies segment_id of a current block to be encoded, and encodes the current block using the at least one parameter defined for identified segment_id. The at least one parameter includes seg_context_idx for identifying probability information associated with context used in context-based adaptive binary arithmetic coding (CABAC).
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: March 19, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventor: Tatsuhiko Ikeda
  • Patent number: 10224947
    Abstract: Embodiments of the present invention provide a digital-to-analog conversion circuit, where the digital-to-analog conversion circuit includes a signal amplitude detector and a digital-to-analog converter. When the signal amplitude detector detects a low signal amplitude, a first current module in the digital-to-analog converter operates normally and a second current module in the digital-to-analog converter stops operating. In addition, when stopping operating, the second current module is in a state of a third bias voltage and a fourth bias voltage that are generated by a second bias circuit. When the amplitude detector detects a high signal amplitude subsequently, the second current module resumes normal operation. After operating normally, the second current module switches back to a first bias voltage and a second bias voltage that are generated by a first bias circuit. This reduces a nonlinearity problem caused before a second current module resumes normal operation.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: March 5, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ding Li, Shuai Du, Hongpei Wang
  • Patent number: 10218382
    Abstract: The following description is directed to decompression using cascaded history buffers. In one example, an apparatus can include a decompression pipeline configured to decompress compressed data comprising code words that reference a history of decompressed data generated from the compressed data. The apparatus can include a first-level history buffer configured to store a more recent history of the decompressed data received from the decompression pipeline. The apparatus can include a second-level history buffer configured to store a less recent history of the decompressed data received from the first-level history buffer.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: February 26, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Ori Weber, Ron Diamant, Yair Sandberg
  • Patent number: 10211536
    Abstract: An antenna structure includes a housing, a first connecting portion, a matching unit, a second connecting portion, and a first switching circuit. The housing defines a slot, a first gap, and a second gap. The housing is divided into a first portion and a second portion by the slot, the first gap, and the second gap. The second portion is grounded. One end of the first connecting portion electrically connected to the first portion and another end of the first connecting portion electrically connected to a feed point through the matching unit. The first portion is divided into a first radiating portion and a second radiating portion by the first connecting portion. One end of the second connecting portion is electrically connected to the first radiating portion and another end of the second connecting portion is grounded through the first switching circuit.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: February 19, 2019
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Chia-Ming Liang, Sheng-Chieh Liang, Ming-Yu Chou, Chang-Hsin Ou, Cheng-I Chang
  • Patent number: 10205465
    Abstract: Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: February 12, 2019
    Assignee: Intel IP Corporation
    Inventors: John G. Kauffman, Krzysztof Dufrene
  • Patent number: 10200059
    Abstract: A device includes a resistor string that includes a plurality resistors with voltage taps disposed therebetween. The device may select one particular voltage tap of the plurality of voltage taps based on received gray level data for a pixel of a display. The device also includes a first amplifier that may be coupled to a first terminal end of the resistor string. The device additionally includes a second amplifier that may be coupled to a second terminal end of the resistor string, wherein the plurality of voltage taps may each supply a tap voltage derived from a voltage between the first amplifier and the second amplifier, wherein any tap amplifier of the device coupled to a voltage tap of the plurality of voltage taps provides a reference voltage thereto.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: February 5, 2019
    Assignee: APPLE INC.
    Inventors: Baris Cagdaser, Derek K. Shaeffer, Hopil Bae, Jesse Aaron Richmond, Jie Won Ryu, Kingsuk Brahma, Mohammad B. Vahid Far, Shingo Hatanaka, Yafei Bi, Yuichi Okuda
  • Patent number: 10199738
    Abstract: An electromagnetic device includes: a first medium having a first material having a first dielectric constant, the first medium having a plurality of spaces filled with a second material having a second dielectric constant that is different from the first dielectric constant; and a plurality of antennas disposed proximate the first medium; wherein adjacent ones of the plurality of spaces of the first medium have an average spacing therebetween of less than one quarter of an operating wavelength of at least one of the plurality of antennas.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 5, 2019
    Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Raymond C. Rumpf, Cesar R. Garcia
  • Patent number: 10177438
    Abstract: A multi-band radiating array includes a planar reflector, first radiating elements defining a first column on the planar reflector, second radiating elements defining a second column on the planar reflector alongside the first column, and third radiating elements interspersed between the second radiating elements in the second column. The first radiating elements have a first operating frequency range, the second radiating elements have a second operating frequency range that is lower than the first operating frequency range, and the third radiating elements have a third, narrowband operating frequency range that is higher than the second operating frequency range but lower than the first operating frequency range. Respective capacitors are coupled between elongated arm segments and an elongated stalk of the third radiating elements, and a common mode resonance of the third radiating elements is present in a lower frequency range than the second operating frequency range.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: January 8, 2019
    Assignee: CommScope Technologies LLC
    Inventors: Jing Sun, Ligang Wu, Hangsheng Wen, Martin Zimmerman
  • Patent number: 10175655
    Abstract: An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Tarun Mahajan, Dheeraj Shetty, Ramnarayanan Muthukaruppan
  • Patent number: 10164339
    Abstract: A communication device includes an antenna system. The antenna system at least includes a dual-polarized antenna, a reflector, and a PIFA (Planar Inverted F Antenna). The dual-polarized antenna includes a first diamond-shaped dipole antenna element and a second diamond-shaped dipole antenna element. The second diamond-shaped dipole antenna element has two truncated tips. The reflector is adjacent to the dual-polarized antenna, and is configured to reflect the radiation energy from the dual-polarized antenna. The PIFA is at least partially formed by the reflector. The PIFA includes a radiation element, a grounding element, and a feeding element. A slot is formed between the radiation element and the grounding element. The slot has a varying width, so as to increase the operation bandwidth of the PIFA.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: December 25, 2018
    Assignee: WISTRON NEWEB CORP.
    Inventors: Chieh-Sheng Hsu, Cheng-Geng Jan
  • Patent number: 10164654
    Abstract: A data compressing device according to an embodiment includes a data cutting unit configured to divide continuously inputted data into W-bit data blocks and to output the data blocks in segments such that each of the segments is composed of N data blocks, and a compression-method determining unit configured to select, as a compression portion for each of the segments, a run length system, a flag system, or no compression, according to a ratio of data blocks of specific data in any of the segments. The data compressing device further includes an RL compression unit configured to execute, on any of the segments, a run length system of storing a consecutive amount of the specific data into compressed data, and a flag compression unit configured to execute, on any of the segments, a flag system of storing positional information of the specific data into compressed data.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 25, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuki Inoue, Keiri Nakanishi, Yasuki Tanabe, Wataru Asano
  • Patent number: 10158859
    Abstract: A data compression apparatus is described which has an encoder configured to receive an input data item and to compress the data item into an encoding comprising a plurality of numerical values. The numerical values are grouped at least according to whether they relate to content of the input data item or style of the input data item. The encoder has been trained using a plurality of groups of training data items grouped according to the content and where training data items within individual ones of the groups vary with respect to the style. The encoder has been trained using a training objective which takes into account the groups.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: December 18, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sebastian Nowozin, Ryota Tomioka, Diane Bouchacourt
  • Patent number: 10158372
    Abstract: An analog-to-digital converter (“ADC”) includes an analog voltage sampler having an energy storage device, such as a capacitive element, configured to charge based on an analog input voltage. A timer determines an elapsed time for the energy storage device to discharge to a predetermined value. The ADC outputs a digital value representing the analog input voltage based on the determined elapsed time.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFCTURING COMPANY, LTD.
    Inventors: Eric Soenen, Alan Roth
  • Patent number: 10141946
    Abstract: A system may include an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a variable resistor coupled to the output and having a plurality of modes including a first mode in which the variable resistor has a first resistance and a second mode in which the variable resistor has a second resistance, and control circuitry configured to determine a difference between the input signal and the output signal and switch between modes of the plurality of modes when the difference is less than a predetermined threshold.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: November 27, 2018
    Assignee: Cirrus Logic, Inc.
    Inventors: Ramin Zanbaghi, Daniel J. Allen, John L. Melanson, Aniruddha Satoskar, Akshay Godbole
  • Patent number: 10141650
    Abstract: An antenna module includes a multilayer body of laminated insulator layers, surface-mounted devices on a top surface of the multilayer body, an antenna coil with a coil winding axis extending in the laminating direction of the insulator layers or in a direction parallel or substantially parallel to the insulator layers, and wiring conductors electrically connected with the surface-mounted devices or the antenna coil. The antenna coil includes coil conductors on more than one of the insulator layers, and interlayer connection conductors, each of which electrically connects end portions of corresponding ones of the coil conductors to each other, to define a helical shape. The wiring conductors are within a space defined through formation of the antenna coil, in the laminating direction of the insulator layers.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: November 27, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Nobuyuki Tenno
  • Patent number: 10133453
    Abstract: In an implementation, a mobile communications device includes a display device having touchscreen functionality, a keyboard having a plurality of physical keys that include a dedicated key and letter keys arranged according to a QWERTY layout, and one or more modules. The one or more modules are configured to output a user interface on the display device responsive to selection of the dedicated key, the user interface having a plurality of portions that are selectable via the touchscreen functionality to cause input of a respective one of a plurality of emoticons.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: November 20, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: David Henry Wykes, Catherine Sayim Kim, Audrey Louchart, Michael J. Kruzeniski, Kathleen W. Holmes, Jonathan D. Friedman, Joseph P. Marquardt
  • Patent number: 10128860
    Abstract: A method of increasing SAR ADC conversion rate and reducing power consumption by employing a new timing scheme and minimizing timing delay for each bit-test during binary-search process. The high frequency clock input requirement is eliminated and higher speed rate can be achieved in SAR ADC.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: November 13, 2018
    Assignee: IPGreat Incorporated
    Inventors: Yuan-Ju Chao, Ta-Shun Chu
  • Patent number: 10101709
    Abstract: A time register includes: a pair of inputs coupled to a pair of input clocks; a pair of tri-state inverters for producing a pair of level signals; and a pair of outputs coupled to the level signals for producing a pair of output clocks, wherein the tri-state inverters are responsive to a pair of state signals and the pair of input clocks for holding or discharging the level signals.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: October 16, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Ying Wu, Robert Bogdan Staszewski, Yihong Mao
  • Patent number: 10097192
    Abstract: Circuits and methods for current recycling in signal buffers for switched capacitor circuits are described. A signal buffer may be coupled to an impedance element, such as a resistor, configured to provide a desired reference voltage to the switched capacitor circuit. In some embodiments, a portion of the power absorbed by the impedance element may be recycled to power one or more additional circuit. Such additional circuit(s) may include active elements. In some embodiments, the switched capacitor circuit is part of an analog-to-digital converter. In some embodiments, the additional circuit(s) are also part of the analog-to-digital converter.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: October 9, 2018
    Assignee: MediaTek Inc.
    Inventor: Jen-Huan Tsai
  • Patent number: 10097200
    Abstract: A device having a sample-rate converter that may be programmed to generate samples at different rates is synchronized to an external synchronization pulse by temporarily changing the sample rate to a temporary sample rate and then changing the sample rate back to the original sample rate. Synchronization in a reduced amount of time is achieved by determining the interval between the synchronization pulse and one of the output samples and determining a processing time of the device for generating the output samples at a new rate. The system calculates a temporary sample rate based on these calculations that tends to reduce an amount of time to achieve synchronization.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: October 9, 2018
    Assignee: Analog Devices Global
    Inventors: Miguel Usach Merino, Michael Hennessy, Anthony Evan O'Shaughnessy, Claire Croke