Abstract: A handheld electronic device may be provided that contains a conductive housing and other conductive elements. The conductive elements may form an antenna ground plane. One or more antennas for the handheld electronic device may be formed from the ground plane and one or more associated antenna resonating elements. Transceiver circuitry may be connected to the resonating elements by transmission lines such as coaxial cables. Ferrules may be crimped to the coaxial cables. A bracket with extending members may be crimped over the ferrules to ground the coaxial cables to the housing and other conductive elements in the ground plane. The ground plane may contain an antenna slot. A dock connector and flex circuit may overlap the slot in a way that does not affect the resonant frequency of the slot. Electrical components may be isolated from the antenna using isolation elements such as inductors and resistors.

Abstract: Techniques of data compression involve ordering the points of a point cloud according to distance along a space-filling curve. Advantageously, a space-filling curve has the property that points close in distance along the curve are close together in Euclidean space. Thus, differences between points ordered by distance along such a curve, e.g., a Hilbert curve, will be close. When the curve is fractal, i.e., self-similar at all levels, the differences will be small even when the points are very unevenly clustered throughout the point cloud. Such small differences will provide greatly improved compression to the resulting delta-encoded set of points.

Abstract: An IHS chassis houses a wireless communications device with an antenna. A IHS chassis wall includes aesthetic fiber layers that are free of a carbon fiber material and that provide both an inner and outer surface of the chassis wall. A plurality of composite fiber layers are located between the aesthetic fiber layers, with each composite fiber layer including a first fiber layer section with a carbon fiber material, and one or more second fiber layer sections that are free of a carbon fiber material and include a non-carbon fiber material that extends between the carbon fiber material in the first fiber layer section. The one or more second fiber layer sections align to provide one or more wireless transmission windows adjacent the antenna. The carbon fiber material and the non-carbon fiber material may have the same tow size to prevent the appearance of seams.

Abstract: A code converting unit encodes input text data based on an code assignment table stored in a storage device that defines a conversion rule for encoding text data, wherein; the code assignment table being generated by assigning a part of character strings assigned to a 1-byte region of a first code assignment table to a 2-byte region of the code assignment table, and by assigning one or more codes each having two or more bytes to at least a part of character strings assigned to the 2-byte region of the code assignment table.

Abstract: An electronic circuit system with an input for receiving an analog signal having a frequency and comprising noise, that noise including input referred noise, and the noise fluctuates in a range. The system also comprises a signal path with: (i) an analog to digital converter for providing a digital output value in response to a clock period; (ii) a feedback node; and (iii) circuitry for limiting a signal swing at the feedback node, during a period of the clock period, to be no greater than an RMS value of the noise. The analog to digital converter is further for providing the digital output value in response to the analog signal and the signal swing at the feedback node.

Abstract: A system to convert between analog and digital signals, in some embodiments, comprises: a differentiator to produce a differentiated signal based on an input signal and a feedback signal; an integrator, coupled to the differentiator, to integrate the differentiated signal; a quantizer, coupled to the integrator, to quantize the integrated signal; and a low-pass feedback filter, coupled between an output of the quantizer and an input of the differentiator, to generate said feedback signal using the quantized signal, wherein the low-pass feedback filter pushes at least some noise of the quantized signal downward in the frequency spectrum.

Abstract: A method of increasing SAR ADC conversion rate and reducing power consumption by employing a new timing scheme and minimizing timing delay for each bit-test during binary-search process. The high frequency clock input requirement is eliminated and higher speed rate can be achieved in SAR ADC.

Abstract: A method for multi-dimensional modulation of a network protocol including control data and payload data. The method includes encoding a first sine wave with the control data; encoding a second sine wave with the payload data; and summing the first and second sine waves to generate a compound sine wave. In some embodiments, the control data is header information for a first Ethernet packet and post-payload data for a second Ethernet packet; and the payload data is payload data for the second Ethernet packet.

Abstract: A deployable antenna reflector includes a surface cable network formed of a plurality of cables coupled to each other in a mesh pattern. The surface cable network includes at least one rigid rod member that reduces a maximum tensile force caused in the surface cable network.

Abstract: A method, apparatus and system for aligning an antenna reflector with satellites in a satellite configuration.

Abstract: Embodiments of the invention are directed to a device having one or more electromagnetic components embedded in an anisotropic metamaterial (AM) comprising an array of asymmetric unit cells comprising a substrate forming a plurality of channels or spaces having at least one material with different electromagnetic properties included in the channels or spaces in the first material forming an anisotropic metamaterial.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) includes a ring oscillator configured to determine a frequency based on a sampling clock signal and a first control code, and generate an output clock signal having the determined frequency. The SAR ADC further includes a controller configured to generate the first control code based on a count value indicating a number of times of toggling the output clock signal.

Abstract: A parallel-serial conversion circuit including a data transmission unit to output first data and second data of a prescribed pattern in accordance with a second clock obtained by dividing a first clock, a first flip flop to receive the first data so as to output the first data in accordance with the first clock, a second flip flop to receive the second data so as to output the second data in accordance with the first clock, a selector to select one of the first data and the second data so as to output the selected data in accordance with the first clock, and an adjustment unit to compare the second data to be received by the second flip flop and the first data output from the first flip flop so as to adjust, based on a comparison result, a timing for the first flip flop to receive the first data.

Abstract: Embodiments of a multi-channel analog to digital converter (ADC) include: a first multiplying digital to analog converter (MDAC) having: first and second switched capacitor circuit paths respectively coupled between first and second input nodes and an input node of a first gain element, a second MDAC having: third and fourth switched capacitor circuit paths respectively coupled between third and fourth input nodes and an input node of a second gain element, a third MDAC having: fifth and sixth switched capacitor circuit paths respectively coupled between a fifth input node and an input node of a third gain element, seventh and eighth switched capacitor circuit paths respectively coupled between a sixth input node and the input node of the third gain element, the fifth input node coupled to an output node of the first gain element, the sixth input node coupled to an output node of the second gain element.

Abstract: Disclosed examples include pipeline ADC, balancing circuits and methods to balance a load of a reference circuit to reduce non-linearity and settling effects for a reference voltage signal, in which balancing capacitors are connected to a voltage source in a pipeline stage ADC sample time period to precharge the balancing capacitors using a voltage above the reference voltage, and a selected set of the precharged balancing capacitors is connected to provide charge to the output of the reference circuit during the second time period.

Abstract: An apparatus and a method. The apparatus includes a delay processor, a coarse converter and node selector connected to the delay processor and configured to select a first voltage V1 and a second voltage V2 of opposite polarities of adjacent stages of the delay processor, a fine converter connected to the coarse converter and node selector and configured to determine a zero-crossing time associated with the first voltage V1 and the second voltage V2; and an encoder connected to the coarse converter and the fine converter and configured to receive and encode the first voltage V1, the second voltage V2 and the zero-crossing time, wherein V1 is a first negative voltage before the zero-crossing time, and V2 is a first positive voltage after the zero-crossing time.

Abstract: A digital phase locked loop (DPLL) circuit includes a digital-to-time converter (DTC) configured to generate a delayed reference clock signal by delaying a reference clock signal according to a delay control signal and a time-to-digital converter (TDC) coupled to an output of the DTC. The TDC is configured to sample a value of a transition signal according to the delayed reference clock signal and to generate an output signal indicating a phase difference between the delayed clock signal and an input clock signal. A method of controlling a DPLL includes delaying a reference clock signal according to a delay control signal, sampling a value of a transition signal according to the delayed reference clock signal, generating an output signal indicating a phase difference between the delayed clock signal and an input clock signal, and generating a digitally controlled oscillator (DCO) clock signal according to the output signal.

Abstract: The current document is directed to a multi-stage metric-data compression method and subsystem for compressing metric data collected and stored within distributed computing systems to facilitate computer-system management and administration. In a described implementation, metric data is partitioned into constant metric data, low-variability metric data, and high-variability metric data. High-variability metric data is compressed by identifying a set of basis metrics, or independent metrics, with respect to which a remaining set of dependent metrics can be expressed using coefficient multipliers. The high-variability metric data can then be stored as a set of independent metrics and set of coefficients, along with a small amount of additional data.

Abstract: This disclosure relates to compressing and/or decompressing a group of similar data units, such as a table or queue of data units processed by a networking device or other computing apparatus. Each data unit in the group may only have values for fields in a master set. The described systems are particularly suited for hardware-level processing of groups of sparsely-populated data units, in which a large number of the data units have values for only a small number of the fields. In an embodiment, non-value carrying fields in a data unit are compressed based on a compression profile selected for the data unit. The compression profile indicates, for each master field, whether the compressed data unit includes a value for that field. Non-value carrying fields are omitted from the compressed data unit. The compression profile also permits compression of value-carrying fields using variable-width field lengths specified in the profile.

Abstract: This invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure definition including a starting empty cell; one or more path definitions defining paths through the data structure; a character reading and writing engine for writing a binary character to an empty cell with a predefined initial position; a next cell determination engine for determining a next empty cell by methodically checking cells along one of the paths in the data structure until an empty cell is located; a loop facilitator for looping back to the writing next character step and the determining next cell step until there are no more data characters or a next empty cell is not determined; and a serialization deserialization engine for methodically serializing the data structure into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.