Abstract: Integrated circuits contained in a rail are passed through cylindrical electrodes. Two electrodes are connected to an oscillator to transmit out of phase fields. A receiving electrode's output has the residual oscillator frequency component removed by a nulling network and summation device, whose output is fed to a band pass amplifier and balanced demodulator, which receives a phase shifted input from the oscillator. Demodulator output components at and above the oscillator frequency are removed by a low pass filter. A demodulator output above the reference voltage triggers a counter.

Abstract: Odometer having a readout of the light-emitting diode type for showing accurate mileage and having means for introducing a predetermined mileage and selecting an increasing or decreasing mode of operation.

Abstract: To ensure continuous uninterrupted operation of an a-c line voltage-energized microcomputer in the event of a power failure, the line voltage is effectively sensed and in response to a substantial reduction thereof battery power is supplied to the microcomputer before such a reduction can adversely affect the operation of the microcomputer.

Abstract: A repeatedly operable timer is adapted such that preselected time information is reloaded automatically upon lapse of that preselected time information. There are provided an input unit for introduction of preselectable time information, a first and a second storages for storing the same preselectable time information introduced, a subtractor effecting subtraction at a given interval on the time information stored in the first storage, a detector which detects if the time information in the first storage reaches zero as a result of the subtraction, and a control which permits the time information in the second storage to be transferred into the first storage in response to the output of the zero detector.

Abstract: A decision making control circuit responsive to a digital data stream. A control output is provided in response to detection of a predetermined number of successive digital words in the data stream representing numbers having a magnitude greater than a threshold magnitude. Once the control output is provided, a predetermined number of successive words in the data stream must have a magnitude less than the threshold magnitude to terminate the control output.

Abstract: In a data protection apparatus for a multiple CPU system having a common or multiported bulk memory, an interface structure is associated with each of the CPU's. The interface structure cooperates with a firmware engine which is, in turn, a part of the interface control means which controls the transfer of data between the common bulk memory apparatus and each of the several CPU's in the system. Signals generated by the individual CPU's indicative of an emergency situation are applied as input signals to the interface structure. The interface structure then translates those signals into an attention flag signal and signals identifying the source or nature of the emergency. The firmware engine then responds to those signals and effects the necessary measures to protect the data relative to the affected CPU.

Abstract: A frequency counting apparatus is advantageously utilized as a frequency counter for displaying in a digital manner the frequency being received by a radio receiver. The inventive frequency counting apparatus includes a quartz resonator adapted to oscillate at the frequency of 2.sup.n Hz where n is a positive integer, for example 32,768 Hz, and a microprocessor including a programming unit, an operating unit for making operation in accordance with a program of the programming apparatus, a counter and a control unit. The program steps of the programming unit are made to progress based on the oscillation output signal of the quartz resonator. The counter is supplied with a local oscillation signal of a radio receiver. The local oscillation signal supplied to the counter is gated for a predetermined time period determined in accordance with the program of the programming unit, whereby the local oscillation signal is counted.

Abstract: A multi-processor system wherein a plurality of priority-designated central processor units (CPUs) are interconnected by a program control memory which operates to transfer control (linkage) information between CPUs in response to interrupt commands to enable the total processing capacity of the system to be allocated to the highest priority jobs. Each processor unit employs a job swapping control program which responds to an interrupt command from an external source or from a higher priority unit to cause program status data stored in the CPU to be transferred to the program control memory for holding or for passage to a lower priority CPU. The job swapping program also causes program status data from the higher priority CPU to be transferred from the control memory to the CPU to enable processing of a new job. On completion of the interrupt cycle, the control program effects exchange of status data to restore job assignments to the original CPUs.

Abstract: An air flow sensor is disposed in the main supply line of a train air brake system. Circuitry is connected to the sensor and initiates the incrementing of a counter upon the sensing of an air flow rate above a predetermined level for greater than a predetermined length of time. The counting is terminated upon application of the locomotive brakes. The counter thereby produces an indication of elapsed time between the time of an air brake leak occurrence and the time the decrease in pressure is sensed by the locomotive. This indication can be converted to feet based upon speed of travel of the pressure head and divided by the average length of cars in the train to provide an accurate estimate of the location of the leak.

Abstract: A series of holes spaced along the length of a web is sensed optically and corresponding pulses are counted in a first counter. Simultaneously a running web length measurement is performed by an encoder wheel, which supplies encoder pulses to a second counter that counts down from a preselected number. When the count in the first counter reaches a selected value, the count in the second counter represents deviation of a measured "board length" from a standard, which is displayed digitally. A display indicates whether the deviation from the standard is inside or outside of a selected range and, if outside, indicates whether the measured web length is shorter or longer than a standard length. Hole simulation pulses are generated to compensate for missing hole pulses, and data readout is inhibited if the final count in the first counter is produced by a hole simulation pulse. A strobe inhibit circuit avoids errors when a strobe light is used to inspect the web.

Abstract: An LSI microprocessor comprising an instruction fetch portion and an instruction execute portion which fetches an instruction and executes an instruction independently of each other under a microprogram control, a pipeline control being made while synchronizing the portions, the instruction fetch portion containing therein an error processing circuit, which receives an external memory error signal concerning a main memory and an internal protect error signal and which delivers a reset signal for clearing a microprogram counter and starting an error processing microprogram.

Abstract: Disclosed is a data processing system comprising means for storing a plurality of macroinstructions and data, means for determining a starting address of data participating in practice of a macroinstruction read out from the storing means and the entire length of said data in response to said read-out macroinstruction and reading out said data from said storing means based on the thus determined address and entire length, means for shifting the read-out data by a quantity determined by said macroinstruction and means for masking a part, determined by said macroinstruction, of said shifted data, wherein practice of macroinstructions is controlled by a microinstruction sequence, an align field is disposed for these microinstructions to control said read-out means, shifting means and masking means, said shifting means is arranged so that said shifting quantity is determined in response to said starting address and said align field, and means for putting out mask pattern signals indicating the position of data to

Abstract: In a data processing system which includes a central processing unit and one or more main memory units for storing program software instructions and program data, logic is provided within the CPU to signal the main memory units, comprised of semiconductor random access memory chips, that a memory refresh operation can be performed. The logic is organized such that the memory refresh operation signal may be given to the main memory units in parallel with and without detracting from other CPU operations. Further, logic is provided within the CPU to interrupt the CPU normal processing and perform a memory refresh operation if one has not been performed with a predetermined time period. Logic is provided within each main memory unit to accept the memory refresh signals from the CPU and to discard those memory refresh signals that would refresh the memory more frequently than required to retain the memory contents thus reducing main memory power consumption.

Abstract: A counter comprises two housing parts which are a push fit together; two shafts located at their ends within recesses of one housing part and carrying, respectively, conventional number wheels and transfer pinions; a pawl rotatable about the transfer pinion shaft and engaging ratchet teeth on the first number wheel and a solenoid sub-assembly having an armature pivoting about an axis parallel with the transfer pinion axis for reciprocating the pawl. The solenoid sub-assembly is located by grooves and other elements formed inwardly of the housing and does not need to be riveted, screwed or otherwise rigidly secured.

Abstract: Diagnostic circuitry for use with the processor of a data processing system. The diagnostic circuitry includes a control register execution log for receiving control store addresses from a control register associated with an "EXECUTE+1" stage. A log pointer addresses the log when control store addresses are written into or read from the log. Test registers connected to the log and log pointer provide control store addresses and decrementing log addresses when the contents of the log are examined. One of the test registers is also used to hold a control store address for comparison with control store addresses of executing microinstructions, and when a match occurs, to generate a SYNC signal.

Abstract: A method and apparatus for permitting an existing computing system to understand and operate upon applications programming, which has been prepared using the instruction set of another computing system. Selected memory units located in the central processing unit of the existing computing system are removed and apparatus containing a circuit is inserted into the electrical connections previously occupied by such memory units. The inventive circuit contains advanced micro-circuits which provide additional memory capability for containing an inventive microprogram which contains the instruction set of the computing system being emulated. The invention, after installation, permits an existing computing system to operate on applications programming written either in its original language or in the language of the machine being emulated.

Abstract: A multi-function type sheet counting machine capable of counting sheets under a desired operational mode selected from a plurality of operational modes. As the sheets to be counted are deflected one after another away from a stack of sheets, electrical count pulses corresponding to the number of deflected sheets are generated, and a count corresponding to the number of generated pulses is stored in a counter. A reset circuit is provided so that, at the time of changing over to the add mode from any other operational mode, the counter is automatically reset to clear the count previously stored in the counter.

Abstract: A method and apparatus for high-speed searching of a byte stream for predetermined words or terms. More particularly, the present invention is directed to a method and apparatus for use in combination with a data source supplying a stream of binary signals defining both the identities of alphanumeric characters occurring in an ordered sequence and the position of each such character within a character group for detecting the occurrence of a particularly ordered group of R characters. The apparatus preferably includes a search memory means comprised of multiple (N) sets of R storage locations each of which includes S bit stages, each bit stage being capable of storing a "1" or "0" state. R represents the number of characters within a character group and S represents the number of different characters that can be identified. Each of the R storage locations may store one or more "0" bits, the position of each "0" bit identifying a particular character.

Abstract: The device comprises a magazine for a stack of sheets, a sheet-extracting head which can be connected to a vacuum source and is rotatably mounted on a turntable which carries a number of columns, and means for counting the number of revolutions performed by the turntable. A first safety device indicates whether the sheet-extracting head has taken more than one sheet and a second safety device checks whether the extracting head has in fact taken at least one sheet. A circular sector of the first safety device is pivotally mounted on the extracting head. The radius of the sector is equal to the distance between its geometrical axis and the cylindrical surface of the next column increased by a value between the thickness of a single sheet to be counted and the sum of thicknesses of two sheets.

Abstract: A data communication system having a master unit, an interface, and one or more remote units. The master unit includes a programmable controller having a data processor, memory storage for storing programs and command and data bytes, and address and data buses. The interface is connected to the master unit via the address and data buses, and includes a memory connected to the data bus for temporarily storing command and output data bytes from the master unit pending transmittal thereof to the remote units and for storing input data bytes from the remote units pending transfer thereof to the master unit. A first communication path, along which command and data bytes from the interface memory are transmitted to the remote units, couples the interface with the remote units. A second communication path, along which input data bytes from the remote units to the interface memory are transmitted, couples the remote units with the interface.