Abstract: A user interactive method of operating a computer is provided for producing a user-weighted ordinal rank order preference scale of rank ordered expression alternatives associated with a plurality of expressions. In the preferred method, the user interacts with the computer system to initially rank all of the alternatives and then assigns point values to the alternatives whereupon the computer calculates a point value weight for each factor level.

Abstract: A method and system for addressing memory of an information handling system in which the memory comprises a plurality of memory banks, each of which can support a plurality of different predetermined size memory modules. The sizes of the different modules are multiples of the module having the smallest size. In the embodiment described, two different sizes are employed, a 256K capacity module and a 1 Meg. capacity module, either of which can be installed in 1 of 4 memory banks. The maximum addressable address range is therefore 4 Meg. while the minimum memory is 256K. The address range can be increased in increments of 256K corresponding to 1 segment to a total of 16 contiguous segments or 4 Meg. A memory address bus comprising 22 lines is employed in the system. The 20 low order lines address each bank simultaneously. A converter converts the 4 high order address bits 22-19 to 16 sequentially ordered segment lines.

Abstract: In a user-interactive display-based telephone system, the present invention permits an automatic display of a repertoire of telephone command items most likely to be utilized by a user, thus providing one-touch access to such item without requiring either explicit programming of a command repertoire or a search by the user through the history of previous commands. This is accomplished through the use of three heuristics which consider frequency of command use, recency of command use, and previously failed commands. These heuristics may be implemented either separately or together in the system.

Abstract: A multi-window display control system, which is constructed so that a plurality of terminals having a multi-window display are connected through a terminal controller with a processor having a high priority and a processor having a low priority. One of the terminals is assigned as a common terminal displaying messages coming from either of the processors. The terminal controller is provided with a save buffer. The frequency of use of each of the virtual screen buffers of the common terminal is stored. When a message coming from the processor having a high priority is received, the virtual screen buffer, whose frequency of use is the lowest, is selected among the virtual screen buffers of the common terminal. The message is stored in the selected virtual screen buffer after having saved the content of the selected virtual screen buffer in the save buffer.

Abstract: A method for developing computer program external interfaces by simulating the interfaces to allow intended users to evaluate the design of the program, even before program code for the simulated program is created.The interfaces are executed as a simulated program. During execution, the interfaces may be altered; execution can then continue using the altered interfaces.

Abstract: A system for maintaining data consistency among distributed processors, each having its associated cache memory. A processor addresses data in its cache by specifying the virtual address. The cache will search its cells for the data associatively. Each cell has a virtual address, a real address, flags and a plurality of associated data words. If there is no hit on the virtual address supplied by the processor, a map processor supplies the equivalent real address which the cache uses to access the data from another cache if one has it, or else from real memory. When a processor writes into a data word in the cache, the cache will update all other caches that share the data before allowing the write to the local cache.

Abstract: A telemetry data processor for processing extremely high bandwidth data such as that associated with telemetry from spacecraft. A demultiplexer (1) distributes the data onto several channels (CHl through CHn), each comprising a (preferably split-cycle synchronous) processing bus (BUSl through BUSn). Processing can occur on each of the n buses simultaneously. Several processor modules (P boards) are directly coupled to each processing bus, with each P board directly coupled to two buses. Several memory modules (M boards) are directly coupled to each processing bus, with each M board directly coupled to two buses. The functions and architectures of the P boards and M boards are described, along with those of D boards (disk controller modules) and I boards (modules for interfacing the telemetry data processor with its outside environment, which may comprise local area networks, peripherals, gateways, etc.).

Abstract: An electronic circuit board electrically connected to other circuits of a data processing system by means of a bus, may be removed and re-inserted in the system without the necessity of disabling other circuits connected to the bus. A latch actuated switch provides a control signal in anticipation of circuit board removal. The control signal activates a finite state machine which seizes control of the bus after completion of any current bus communications and stops the generation of clock pulses normally required in bus communications. When contact is physically broken between the board and its corresponding connector, the finite state machine restores the bus clock pulses and relinquishes control of the bus. When a board is to be inserted in an open connector, contact between the board and the connector is sensed by the finite state machine which causes the bus to be seized and the bus clock pulses to be temporarily inhibited.

Abstract: In a database having a dictionary/directory, the dictionary/directory is processed to form a directory using information in the dictionary, or is processed for other purposes. A process record including identification information associated with the process is stored in the dictionary/directory. In a dictionary deletion process, the stored record is designated and read out such that associated information indicated by the process record is also deleted in a batch manner.

Abstract: A memory initialization system for initializing a memory content in response to a memory initialization instruction is disclosed. In this system, a memory initialization instruction validity control means for controlling validity of the memory initialization instruction is arranged. The memory initialization instruction validity control means can render the memory initialization instruction invalid so as to inhibit initialization for the memory.

Abstract: A program generator automatically generates a program based on a flow-chart of a series of sequence control processes. The flow-chart is prepared while being displayed on the display area of a display means such as CRT, and when the flow-chart is complete, a program is automatically generated corresponding to the flow-chart.

Abstract: A data load serializer for use in conjunction with a multi-stage, multiple parallel data channel serializer is described. Each data channel of the data serializer preferably includes a data sensing stage and a data latching stage. The serializer is preferably responsive to the provision of an address for selecting data from the main buffer memory for provision to the serial buffer memory and further preferably includes sequencer control logic for receiving the main buffer memory address and for directing the transfer of data between the main and serial buffer memories and an address counter for receiving a start location address referencing a beginning serial data buffer memory location of the storage of data sourced to or from the data serializer.

Abstract: A spelling check module for use in conjunction with an electronic typewriter or personal computer of the type which has a keyboard and a data processor interconnected by a respective keyboard connector and a data processor connector, includes male and female connectors which are arranged to receive the keyboard connector and data processor connectors. The spelling check module is installed by disconnecting the keyboard connector from the data processor connector and interposing the spelling check module therebetween by connecting the keyboard connector and the data processor connector to the respective connectors of the spelling check module. The spelling check module is controlled by selected non-printing, non-control keys, and also includes a personal dictionary to which dictionary words can be added by the user to customize the spelling check module to a specific application.

Abstract: A vector processing system is provided, including a store data alignment circuit for a pipe line structure and improving an access time for storing vector-processed data in main storage units connected thereto. The vector processing system includes: a unit for storing vector-processed data; a unit for controlling the reading of the vector-processed data from the vector-processed data storing unit, and the storing of the read data in the main storage units; a unit correspondingly provided to the main storage unit, for receiving the vector-processed data through the read and store control unit and buffering the data therein; a unit for managing the data stored in the data buffering unit; and a unit for determining a priority of a store access to the main storage unit. The read and store control unit and the main storage unit are operable in response to the priority determined by the priority determining unit.

Abstract: A video memory system which uses dynamic digital data storage elements allows random access to blocks of 32 pixel values. The pixel values to be stored in a block are applied sequentially to the memory system and the pixel values provided by the memory system are provided sequentially. The block oriented random access memory which stores and provides the blocks of 32 pixel values is configured to be able to perform a block read, a block write and a refresh operation in the time required to provide one 32 pixel block to or from the video memory system.

Abstract: An indexed sequential file is made accessible for random or sequential reading of records while allowing concurrent modification to the file. Each ordered group of records in the file is associated with timestamps referencing a deletion time of the group and the time that the group was last modified. During a current search in a group for a desired record, the timestamp referencing a deletion time of the group is compared to a search time established at the beginning of the search. For a sequential reading the timestamp referencing a last modification time of a group containing the desired record is compared to a respective timestamp corresponding to the reading of the preceeding record. The comparisons provide indications of whether the group to which the desired record belongs is currently the group to be searched. The most recently modified and deleted groups are stored in a cache memory.

Abstract: A dual port digital memory system, which includes integral memory sequencing circuitry, is controlled by a bit-serial address and control signal. The address and control signal, which includes a data read address, a data write address and a control value, is serially loaded into a shift register. The address sequencing circuitry loads the read and write address values into integral read and write address registers and, based on the control value, initiates respective read and/or write operations.

Abstract: The apparatus controls access to at least one subsystem in response to requests for access from a plurality of equipments operatively connected to a corresponding port of said apparatus. The requests for access have a plurality of command levels wherein the command levels have a fixed predetermined priority relative to each other. The apparatus comprises a plurality of port request control elements for generating a plurality of specific request signals including a command level request signal to indicate the command level of a request received from the corresponding equipment, and a go signal to indicate the availability of the apparatus and the subsystem in order to execute the command requested. An activity priority select control element receives the specific request signals, and processes the go signals from each of the port request control elements to grant access within a predetermined time period to the equipment connected to the port having the highest port priority within the highest command level.

Abstract: A computer is sped up by reducing significantly the time necessary for the computer to detect and respond to an overflow following an ALU operation of a type which generates an overflow. This is done by assuring the next instruction in sequence is the one to be executed and in parallel detecting the occurrence of an overflow as the result of an implementation of a selected instruction and then producing a flag in response to the overflow. The flag is detected, and selected portions of the computer are disabled to inhibit any change in state within the computer following the generation of the overflow. An interrrupt sequence is then implemented to correct the output of the instruction which generated the overflow to compensate for the overflow. The next following instruction is then implemented after completion of the interrupt routine.

Abstract: Two circuit arrangements are described for transforming 2.sup.n global addresses used in a control engineering system having several local units into 2.sup.m local addresses used in one of the units of the system. One of these contains several memories in which subfunctions resulting from a splitting of the transformation function conveying the transformation are stored. The other circuit arrangement contains a single memory which accepts all subfunctions. The transformation function is split into the subfunctions in such a manner that an optimum compromise is achieved between the storage space required for storing the subfunctions and the time required for the transformation.