Patents Examined by Julia Slutsker
  • Patent number: 10811446
    Abstract: Disclosed are an array substrate and a manufacturing method therefor, a display panel and a display device, which are used for enabling a viewer to see a uniform reflective effect at various viewing angles, improving the display effect. The array substrate manufacturing method comprises: sequentially forming, on a passivation layer, a reflective layer and a transparent conductive layer, the reflective layer being electrically connected, by means of a via hole penetrating through the passivation layer, to a source electrode or a drain electrode of the thin film transistor, and the transparent conductive layer comprising several metal ions; performing reduction process on the transparent conductive layer, so that the metal ions are reduced, and a metal particle layer is formed; and performing patterning process on the transparent conductive layer and the reflective layer on which the steps above are completed, so as to form a pixel electrode.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: October 20, 2020
    Assignees: Hefei BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Kui Gong, Xianxue Duan, Myoung Kee Baek
  • Patent number: 10804136
    Abstract: Semiconductor fins of a monolithic semiconductor structure are electrically isolated using a dielectric material at the bottoms of the fins. Relatively tall semiconductor fins can be fabricated at a relatively narrow fin pitch while avoiding mechanical instability. The semiconductor fins are grown on sidewalls of semiconductor mandrels and over a dielectric layer. The semiconductor fins are supported during mandrel removal to provide mechanical stability. The semiconductor fins can be employed as channel regions of FinFET devices.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Chun-Chen Yeh, Tenko Yamashita, Ruilong Xie
  • Patent number: 10804200
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Patent number: 10797162
    Abstract: The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: You-Ru Lin, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 10797136
    Abstract: A preparation method for a multilayer graphene quantum carbon-based two-dimensional semiconductor material comprises: S1. taking a PI film as a raw material, and performing polymer sintering at a first temperature, to remove H, O and N atoms to form a carbon precursor; and S2. adjusting the temperature to a second temperature, and graphitizing the carbon precursor to form a multilayer graphene quantum carbon-based two-dimensional semiconductor material, wherein in at least the step S2, a nano metal material is doped to form quantum dots in the multilayer graphene. The multilayer graphene quantum carbon-based two-dimensional semiconductor material prepared by the method adopts a hexagonal planar net molecular structure, is orderly arranged, and has flexibility, high tortuosity, and quite low in-plane dispersity and degree of deviation. Band gaps are formed through doping of a nano metal, and the band gaps are controllable.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: October 6, 2020
    Assignee: SHENZHEN DANBOND TECHNOLOGY CO., LTD
    Inventor: Ping Liu
  • Patent number: 10784426
    Abstract: A device substrate includes a receiving substrate, a micro light emitting element, a first wire, and a second wire is provided. The micro light emitting element is disposed on the receiving substrate. The micro light emitting element includes a first type semiconductor layer and a second type semiconductor layer. The first type semiconductor layer is disposed on the receiving substrate and has a first wire connecting surface away from the receiving substrate. The second type semiconductor layer is disposed on a part of the first type semiconductor layer and has a second wire connection surface away from the receiving substrate. The first wire is disposed on the first wire connection surface. The second wire is disposed on the second wire connection surface. A projection range of the first wire perpendicularly projected on the micro light emitting element and a projection range of the second wire perpendicularly projected on the micro light emitting element are at least partially overlap.
    Type: Grant
    Filed: May 27, 2019
    Date of Patent: September 22, 2020
    Assignee: Au Optronics Corporation
    Inventors: Wen-Wei Yang, Cheng-Chieh Chang, Cheng-Yeh Tsai
  • Patent number: 10784257
    Abstract: This specification discloses methods for integrating a SiGe-based HBT (heterojunction bipolar transistor) and a Si-based BJT (bipolar junction transistor) together in a single manufacturing process that does not add a lot of process complexity, and an integrated circuit that can be fabricated utilizing such a streamlined manufacturing process. In some embodiments, such an integrated circuit can enjoy both the benefits of a higher RF (radio frequency) performance for the SiGe HBT and a lower leakage current for the Si-based BJT. In some embodiments, such an integrated circuit can be applied to an ESD (electrostatic discharge) clamp circuit, in order to achieve a lower, or no, yield-loss.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 22, 2020
    Assignee: NXP B.V.
    Inventors: Petrus Hubertus Cornelis Magnee, Pieter Simon van Dijk, Johannes Josephus Theodorus Marinus Donkers, Dolphin Abessolo Bidzo
  • Patent number: 10784281
    Abstract: A 3D semiconductor memory device includes an electrode structure on a substrate, the electrode structure including gate electrodes stacked in a first direction perpendicular to a top surface of the substrate, a vertical semiconductor pattern penetrating the electrode structure and connected to the substrate, and a data storage pattern between the electrode structure and the vertical semiconductor pattern. The data storage pattern includes first, second and third insulating patterns sequentially stacked. Each of the first to third insulating patterns includes a horizontal portion extending in a second direction parallel to the top surface of the substrate. The horizontal portions of the first, second and third insulating patterns are sequentially stacked in the first direction. At least one of the horizontal portions of the first and third insulating patterns protrudes beyond a sidewall of the horizontal portion of the second insulating pattern in the second direction.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 22, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Heon Kang, Bongtae Park, Jae-Joo Shim
  • Patent number: 10784322
    Abstract: Embodiments of the present disclosure provide an array substrate, a manufacturing method, and a display device. The array substrate comprises: a pixel define layer located on a base substrate, the pixel define layer having a hollow for defining a sub-pixel light emitting area, and a light emitting functional layer located in the hollow, wherein, the pixel define layer has protrusion structures on one or more sides facing the hollow.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 22, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Qing Dai
  • Patent number: 10777664
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions, so that portions of semiconductor strips between the isolation regions protrude higher than the isolation regions to form semiconductor fins. The method further includes recessing the semiconductor fins to form recesses, epitaxially growing a first semiconductor material from the recesses, etching the first semiconductor material, and epitaxially growing a second semiconductor material from the first semiconductor material that has been etched back.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Husan Hung, Guan-Jie Shen, Pin-Cheng Hsu
  • Patent number: 10777471
    Abstract: The disclosed technology generally relates to semiconductor characterization, and more particularly to detecting manufacturing defects in semiconductor regions. In one aspect, a non-destructive method of detecting a manufacturing defect in a semiconductor device includes providing a semiconductor device comprising an electrically isolated conductive via formed in a semiconductor region. The method additionally includes locally heating to cause a temperature change in a volume of the semiconductor region from a first temperature to a second temperature. The method additionally includes applying an electrical bias between the conductive via and the semiconductor region to form a temperature-dependent depletion region in the semiconductor region.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 15, 2020
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Kristof J. P. Jacobs, Ingrid De Wolf
  • Patent number: 10777463
    Abstract: One illustrative device disclosed herein includes an epi cavity formed in a semiconductor substrate adjacent a gate structure of a transistor and an epi semiconductor material comprising first and second portions. The first portion of the epi semiconductor material is positioned within the epi cavity. The second portion of the epi semiconductor material is positioned above the first portion of the epi semiconductor material and above a level corresponding to a level of an upper surface of the semiconductor substrate. The first portion of the epi semiconductor material has a first dimension in a direction corresponding to a gate length direction of the transistor and the second portion of the epi semiconductor material has a second dimension in a direction corresponding to the gate length direction of the transistor, wherein the first dimension is greater than the second dimension.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Man Gu, Tao Han
  • Patent number: 10766778
    Abstract: A polycrystalline material having low mechanical strain is provided. The polycrystalline material includes one or multiple layers of a first type and one or multiple layers of a second type. The layers of the first type and the layers of the second type each include at least one polycrystalline material component. The layers of the first type have a smaller average crystal grain size than the layers of the second type, a layer of the first type and a layer of the second type being situated, at least in part, one above the other in an alternating sequence, and it being the case for the transition between the layers of the first type and the layers of the second type to be abrupt or continuous.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 8, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Andreas Hartlieb, Heiko Stahl, Jochen Beintner, Juergen Butz
  • Patent number: 10763325
    Abstract: A capacitor structure includes an insulative layer, a first electrode over the insulative layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The first electrode includes a first portion extending along a lateral direction of the insulative layer and a second portion connected to the first portion and extending along a depth direction of the insulative layer. The dielectric layer is substantially conformal with respect to a profile of the first electrode. A semiconductor structure thereof and a method for forming the same are also provided.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chih-Kuang Kao
  • Patent number: 10763280
    Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) device, the first FinFET device including a plurality of fins formed in a substrate, an epitaxial layer of semiconductor material formed on the fins forming non-planar source/drain regions, and a first gate structure traversing across the plurality of fins. The semiconductor device includes a second FinFET device, the second FinFET device including a substantially planar fin formed in the substrate, an epitaxial layer of the semiconductor material formed on the substantially planar fin and forming substantially planar source/drain regions, and a second gate structure traversing across the substantially planar fin.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Chen Liu, Guan-Jie Shen, Chia-Der Chang
  • Patent number: 10763352
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having first and second surfaces and an impurity concentration distribution in a first direction from the second surface to the first surface, a first semiconductor region of a second conductivity between the semiconductor layer and the first surface, a second semiconductor region of a first conductivity type between the first semiconductor region and the first surface side, a first trench extending from the first surface into the semiconductor layer, a first electrode located in the first trench over a first insulating film and spaced from the first semiconductor region by a first insulating film, a second electrode located in the first trench over a second insulating film, a second trench extending from the first surface into the semiconductor layer and surrounding the first trench, and a third electrode located in the second trench over a third insulating film.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 1, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroshi Matsuba, Hung Hung, Tatsuya Nishiwaki, Kohei Oasa, Kikuo Aida
  • Patent number: 10747047
    Abstract: A display device includes: a light provider; a wavelength conversion layer above the light provider and including a first surface and sides; and a capping layer on the wavelength conversion layer and including a first area provided on the sides of the wavelength conversion layer and a second area provided on the first surface of the wavelength conversion layer, and the first area of the capping layer includes cracks.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: August 18, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hee Keun Lee, Won Tae Kim, Yeo Geon Yoon, Seung Jin Chu
  • Patent number: 10748980
    Abstract: A display device includes a substrate including a display region, a pad region spaced apart from the display region, and a bending region between the display region and the pad region. A plurality of pixel structures is positioned in the display region of the substrate. A plurality of pad wirings is positioned in the pad region of the substrate. A plurality of connection wirings electrically connect the pad wirings to the pixel structures. The connection wirings include a plurality of notches in the bending region.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Seil Cho
  • Patent number: 10741575
    Abstract: A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: August 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Taek Jung, Joong-Shik Shin, Byung-Kwan You
  • Patent number: 10736217
    Abstract: A surface mounting component module according to one embodiment of the present invention comprises: a multi-layer substrate; a side via formed by penetrating the multi-layer substrate, and electrically connecting the multi-layer substrate; a side via pad positioned on at least one layer of the multi-layer substrate, and formed in the vicinity of the side via; and an RF pattern connected to the side via pad by a signal line, wherein all of the RF pattern, the side via, and the side via pad are electrically connected.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: August 4, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Dong Woo Kim