Abstract: A method of fabricating a semiconductor substrate includes the following steps. A carrier substrate is provided, and a plasma treatment is performed on the surface of the carrier substrate. A polycrystalline semiconductor layer is formed on the surface of the carrier substrate. A rapid thermal treatment is then performed on the polycrystalline semiconductor layer. A buried dielectric layer is then formed on the polycrystalline semiconductor layer. Afterwards, a single crystalline semiconductor layer is formed on the buried dielectric layer.

Abstract: A substrate processing method includes providing a substrate containing a first film, a second film, and a third film, forming a first blocking layer on the first film, forming a second blocking layer on the second film, where the second blocking layer is different from the first blocking layer, and selectively forming a material film on the third film by vapor deposition. In one example, the first film, second film, and the third film are selected from the group consisting of a metal film, a metal-containing liner, and a dielectric film.

Abstract: Superlattices and methods of making them are disclosed herein. The superlattices are prepared by irradiating a sample to prepare an alternating superlattice of layers of a first material and a second material, wherein the ratio of the first deposition rate to the second deposition rate is between 1.0:2.0 and 2.0:1.0. The superlattice comprises a multiplicity of alternating layers, wherein the multiplicity of layers of the first material have a thickness between 0.1 nm and 50.0 nm or the multiplicity of layers of the second material have a thickness between 0.1 nm and 50.0.

Abstract: A method for manufacturing a transition metal-dichalcogenide thin film is provided. The method for manufacturing a transition metal-dichalcogenide thin film can comprise the steps of: preparing a base substrate within a chamber; preparing a precursor comprising a transition metal; repeatedly carrying out, multiple times, a step of providing the precursor on the base substrate and a step of purging the chamber, thereby forming, on the base substrate, a preliminary thin film in which the precursor is adsorbed; and manufacturing a transition metal-dichalcogenide thin film by heat treating the preliminary thin film in a gas atmosphere comprising a chalcogen element.

Abstract: A light-emitting diode device is provided. First and second green conversion materials are respectively configured to convert a blue light emitted from a blue light-emitting diode to generate a first green light with a first wavelength range and a first wavelength FWHM, and a second green light with a second wavelength range and a second wavelength FWHM. The second wavelength FWHM is smaller than the first wavelength FWHM. A lower bound of the first wavelength range is smaller than a lower bound of the second wavelength range, and an upper bound of the second wavelength range is greater than an upper bound of the first wavelength range. An output light emitted from the light-emitting diode device has a spectral characteristic of less than 50% of TÜV Rheinland and more than 90% of wide color gamut.

Abstract: An LED device includes an epitaxial layered structure, a current spreading layer, a first insulating layer and a reflective structure. The current spreading layer is formed on a surface of the epitaxial layered structure. The first insulating layer is formed over the current spreading layer, and is formed with at least one first through hole to expose the current spreading layer. The reflective structure is formed on the first insulating layer, extends into the first through hole, and contacts with the current spreading layer. The current spreading layer is formed with at least one opening structure to expose the surface of the epitaxial layered structure.

Abstract: A semiconductor device includes a transistor. The transistor includes a gate electrode, a channel layer, a gate dielectric layer, a first source/drain region and a second source/drain region and a first spacer. The channel layer is disposed on the gate electrode. The gate dielectric layer is located between the channel layer and the gate electrode. The first source/drain region and the second source/drain region are disposed on the channel layer at opposite sides of the gate electrode, and at least one of the first and second source/drain regions includes a first portion and a second portion between the first portion and the gate electrode. The first spacer is disposed on the channel layer. The first spacer is disposed on a first sidewall of the second portion of the at least one of the first and second source/drain regions, and the first portion is disposed on the first spacer.

Abstract: In an embodiment an apparatus includes a receptacle configured to receive a wafer, a light port configured to emit light from a source of light so as to shine the light on an edge of the wafer, wherein the light port is an opening located on a surface of the receptacle and a light sensitive element configured to receive light that passed the edge of the wafer and to form a detection signal based on the received light, wherein the light port is located underneath the wafer.

Abstract: According to one or more embodiments, a method for manufacturing a semiconductor device comprises forming a stacked film that comprises alternating first insulating layers and second insulating layers. A first insulating film, an electric charge storage layer, a second insulating film, and a first semiconductor layer are then formed in a hole in the stacked film. The method further includes forming a first recess in the stacked film, then supplying a first gas and a deuterium gas to the first recess. The first gas comprises hydrogen and oxygen.

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

Abstract: A semiconductor device includes a semiconductor substrate including a chip region and an edge region around the chip region, a lower insulating layer on the semiconductor substrate, a chip pad on the lower insulating layer on the chip region, an upper insulating layer provided on the lower insulating layer to cover the chip pad, the upper and different insulating layers including different materials, and a redistribution chip pad on the chip region and connected to the chip pad. The upper insulating layer includes a first portion on the chip region having a first thickness, a second portion on the edge region having a second thickness, and a third portion on the edge region, the third portion extending from the second portion, spaced from the first portion, and having a decreasing thickness away from the second portion. The second thickness is smaller than the first thickness.

Abstract: An epitaxial structure, a preparation method thereof, and a light-emitting diode (LED) are provided. The epitaxial structure includes a sapphire substrate, a GaN layer, a defect exposure layer, and a defect termination layer stacked in sequence.

Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.

Abstract: The present disclosure provides systems and methods for processing channel structures of substrates that include positioning the substrate in a first processing chamber having a first processing volume being in fluid communication with a plasma source. The substrate can include a channel structure with high aspect ratio features having aspect ratios greater than about 20:1. The method can also include forming an oxide cap layer over a silicon-containing layer of the channel structure and exposing the oxide cap layer to a hydrogen-or-deuterium radical to nucleate the silicon-containing layer of the channel structures of the substrate. Forming the oxide cap layer and exposing the channel structure with the hydrogen radical occurs in the first processing chamber to form a nucleated substrate. The method can also include positioning the nucleated substrate in a second processing chamber with a second processing volume and heating the nucleated substrate in the second processing chamber.

Abstract: A method of current detection includes providing a transistor arrangement which comprises a drift and drain region arranged in a semiconductor body and each connected to a drain node, a plurality of load transistor cells each having a source region integrated in a first region of the semiconductor body, a plurality of sense transistor cells each having a source region integrated in a second region of the semiconductor body, a first source node electrically connected to the source region of each of the plurality of the load transistor cells via a first source conductor, and a second source node electrically connected to the source region of each of the plurality of the sense transistor cells via a second source conductor; and detecting a first current flowing between the drain node and the first source node of the transistor arrangement, wherein detecting the first current includes measuring a second current flowing between the drain node and the second source node of the transistor arrangement.

Abstract: A method for forming an oxide layer includes forming an interfacial layer on a substrate, forming an amorphous silicon layer on the interfacial layer, performing a direct oxidation process to selectively oxidize the formed amorphous silicon layer, and performing a thermal oxidation process to oxidize the formed amorphous silicon layer.

Abstract: Methods of forming semiconductor devices are provided. The methods include: forming a trench in a substrate, wherein the trench includes a defect protruding from a bottom surface of the trench; forming a flowable material on the substrate to at least partially cover the defect; performing an etching process to reduce the height of the defect; and removing the flowable material.

Abstract: A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10?4 ?cm to 1.0×104 ?cm or a sheet resistance in a range from 1.0×102?/? to 1.0×1010?/?.

Abstract: A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.

Abstract: Embodiments disclosed herein include methods of depositing a metal oxo photoresist using dry deposition processes. In an embodiment, the method comprises forming a first metal oxo film on the substrate with a first vapor phase process including a first metal precursor vapor and a first oxidant vapor, and forming a second metal oxo film over the first metal oxo film with a second vapor phase process including a second metal precursor vapor and a second oxidant vapor.