Patents Examined by Julia Slutsker
  • Patent number: 10446444
    Abstract: An interconnection structure of the semiconductor integrated circuit device may be provided. The interconnection structure may include a first conductive pattern, a second conductive pattern, a dielectric layer and a contact part. The first conductive pattern may have a first width and a first length. The second conductive pattern may be formed over the first conductive pattern. The second conductive pattern may have a second width and a second length. The dielectric layer may be interposed between the first conductive pattern and the second conductive pattern. The contact part may be configured to simultaneously make contact with the first conductive pattern and the second conductive pattern.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: October 15, 2019
    Assignee: SK hynix Inc.
    Inventor: Jong Su Kim
  • Patent number: 10446723
    Abstract: The invention relates to an optoelectronic element comprising a semiconductor chip (12) that emits a blue-green light (4) during operation and has at least one light passage surface (12a) through which the blue-green light (4) emitted during operation passes and comprising a conversion element (3) which comprises fluorescent particles (31), in particular fluorescent particles of only one type, and which is arranged on the light passage surface (12a) at least in some areas. The fluorescent particles (31) at least partly convert the blue-green light (4) into a red light (5), and the optoelectronic element emits a white mixed light (6) which contains non-converted components of the blue-green light (4) and components of the red light (5).
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: October 15, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Rainer Butendeich, Ion Stoll, Martin Mandl, Martin Strassburg
  • Patent number: 10439134
    Abstract: Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: October 8, 2019
    Assignee: INTEL CORPORATION
    Inventors: Prashant Majhi, Elijah V. Karpov, Uday Shah, Niloy Mukherjee, Charles C. Kuo, Ravi Pillarisetty, Brian S. Doyle, Robert S. Chau
  • Patent number: 10434602
    Abstract: The embodiments described herein relate to forming white appearing metal oxide films by forming cracks within the metal oxide films. In some embodiments, the methods involve directing a laser beam at a metal oxide film causing portions of the metal oxide film to melt, cool, contract, and crack. The cracks have irregular surfaces that can diffusely reflect visible light incident a top surface of the metal oxide film, thereby imparting a white appearance to the metal oxide film. In some embodiments, the cracks are formed beneath a top surface of a metal oxide film, thereby leaving a continuous and uninterrupted metal oxide film top surface.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: October 8, 2019
    Assignee: Apple Inc.
    Inventors: Daniel T. McDonald, Michael S. Nashner, Peter N. Russell-Clarke, Masashige Tatebe
  • Patent number: 10439046
    Abstract: The present invention provides for a method of fabricating a semiconductor device, the method includes depositing a nitride layer on an ETSOI layer; forming a dummy gate over the nitride layer; forming nitride gate spacers from the nitride layer; growing a sacrificial layer on the ETSOI layer, the sacrificial layer composing a material that can be at least partially converted to a metal layer by a metal-bearing gas; forming refractory metal contacts using the sacrificial layer and a consumptive process; depositing an oxide protect layer on the refractory metal contacts; removing the dummy gate using a mask and etch process combined with chemical-mechanical polishing (CMP); etching the ETSOI layer to form a U-shaped channel; and depositing the final gate stack into the U-shaped channel.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Dennard, Rajiv V. Joshi, Richard Q. Williams
  • Patent number: 10424666
    Abstract: A semiconductor package includes a leadframe having perimeter package leads and electrical connectors, a single semiconductor die having a back-side electrical contact and front-side electrical contacts, an electrically conductive clip (“clip”), and a top semiconductor die having a frontside and a backside. The single semiconductor die includes two or more transistors. Two or more of the front-side electrical contacts of the semiconductor die are electrically coupled to and physically mounted to respective electrical contacts of the leadframe. An electrical contact surface of the clip is electrically coupled to and physically mounted to an electrical connector of the leadframe. Another electrical contact surface of the clip is physically mounted to and electrically coupled to the back-side electrical contact of the semiconductor die. The backside of the top semiconductor die is physically mounted to yet another surface of the electrically conductive clip.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: September 24, 2019
    Assignee: Silanna Asia Pte Ltd
    Inventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
  • Patent number: 10418466
    Abstract: An object is to provide a high reliability thin film transistor using an oxide semiconductor layer which has stable electric characteristics. In the thin film transistor in which an oxide semiconductor layer is used, the amount of change in threshold voltage of the thin film transistor before and after a BT test is made to be 2 V or less, preferably 1.5 V or less, more preferably 1 V or less, whereby the semiconductor device which has high reliability and stable electric characteristics can be manufactured. In particular, in a display device which is one embodiment of the semiconductor device, a malfunction such as display unevenness due to change in threshold voltage can be reduced.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: September 17, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takahiro Tsuji, Kunihiko Suzuki
  • Patent number: 10411104
    Abstract: Forming a semiconductor device on a semiconductor substrate having a substrate top surface includes: forming a gate trench extending from the substrate top surface into the semiconductor substrate; forming a gate electrode in the gate trench; forming a curved sidewall portion along at least a portion of a sidewall of the gate trench; forming a body region adjacent to the gate trench; forming a source region embedded in the body region, including disposing source material in a region that is along at least a part of the curved sidewall portion; forming a gate top dielectric layer over the gate electrode and having a top side that is below at least a portion of the source region; and forming a metal layer over at least a portion of a gate trench opening and at least a portion of the source region.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: September 10, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: John Chen
  • Patent number: 10411185
    Abstract: A method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. The method includes receiving a wafer having a plurality of bit cells arranged in a grid and etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. The method further includes fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell. The wafer is then planarized. The method further includes etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, and outputting the wafer for subsequent testing.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 10, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Pradeep Manandhar, Prachi Shrivastava, Mustafa Pinarbasi, Thomas Boone
  • Patent number: 10411053
    Abstract: The present disclosure relates to a solid state imaging element and an electronic device that make it possible to improve sensitivity to light on a long wavelength side. A solid state imaging element according to a first aspect of the present disclosure has a solid state imaging element in which a large number of pixels are arranged vertically and horizontally, the solid state imaging element includes a periodic concave-convex pattern on a light receiving surface and an opposite surface to the light receiving surface of a light absorbing layer as a light detecting element. The present disclosure can be applied to, for example, a CMOS and the like installed in a sensor that needs a high sensitivity to light belonging to a region on the long wavelength side, such as light in the infrared region.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: September 10, 2019
    Assignee: Sony Corporation
    Inventor: Sozo Yokogawa
  • Patent number: 10403819
    Abstract: A pixel define layer and manufacturing method thereof and the related light emitting display are disclosed. The pixel define layer is arranged on a conductive layer of a substrate and comprises a base film layer. The base film layer has a plurality of openings each of which corresponds to a light-emitting region of a sub-pixel unit. A spacing base body is formed between the adjacent openings. An upper surface of each spacing base body is coated with a hydrophobic quantum dot material and a side wall of each opening is coated with a hydrophilic quantum dot material. With the pixel define layer and manufacturing method thereof and the related light emitting display according to embodiments of the disclosure, the ink within the sub-pixel would not ooze to the outside of the sub-pixel to result in color mixture between the adjacent sub-pixels, and the light emitting region within the pixel would not be decreased. By selecting suitable quantum dot materials, the photochromic efficiency can be improved.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: September 3, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Hsiao-Wen Hung, Hao-Chih Hung
  • Patent number: 10403658
    Abstract: An image sensing device includes pixels forming rows and columns, sets of control lines respectively assigned to the rows such that one set of control lines is connected to one of the rows, a row drive circuit configured to drive the sets of control lines, and an assist circuit. Each set includes a first control line and a second control line. The row drive circuit includes a first drive circuit connected to a first end of the first control line and a second drive circuit connected to first end of the second control line. The assist circuit includes an assist drive circuit connected to a second end of the first control line so as to drive the first control line in accordance with a control signal supplied to the second control line.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: September 3, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshiaki Takada, Kazuo Yamazaki
  • Patent number: 10403841
    Abstract: An organic EL element is provided that has a high light emission efficiency and that emits a plurality of light beams having respective wavelength ranges different from one another, the light beams including short wavelength light having a high chromaticity. An organic EL element (1) includes an exciton generating layer (7) and a guest layer (8) that are adjacent to each other.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: September 3, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Asae Ito, Yuto Tsukamoto, Manabu Niboshi, Eiji Koike, Shinichi Kawato, Katsuhiro Kikuchi
  • Patent number: 10388653
    Abstract: A production of contact zones for a transistor device including the steps of: a) forming at least one layer made of a compound based on semiconductor and metal on one or more first semiconductor region(s) of a first N-type transistor and on one or more second semiconductor region(s) of a second P-type transistor resting on a same substrate, the first regions being based on a III-V type material whereas the second semiconductor regions are based on another material different from the III-V material, the semiconductor of the compound being an N-type dopant of the III-V material, b) carrying out at least one thermal annealing so as to form on the first semiconductor regions first contact zones and on the second semiconductor regions second contact zones based on a semiconductor and metal compound while increasing the N-doping of the III-V material.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: August 20, 2019
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Rodriguez, Elodie Ghegin, Fabrice Nemouchi
  • Patent number: 10388518
    Abstract: An epitaxial substrate and a method of manufacturing the same are provided. The epitaxial substrate includes a handle substrate, a heat dissipation layer on the handle substrate, a high-resistance silicon substrate on the heat dissipation layer, and a III-V semiconductor layer grown on the high-resistance silicon substrate. The heat dissipation layer has high thermal conductivity. The high-resistance silicon substrate has a resistance more than 100 ohm·cm. Diameters of the high-resistance silicon substrate and the III-V semiconductor film are smaller than a diameter of the handle substrate, such that the epitaxial substrate is a convex substrate.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 20, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Chun-I Fan, Chih-Yuan Chuang, Man-Hsuan Lin, Wen-Ching Hsu
  • Patent number: 10388856
    Abstract: Provided is a magnetoresistance effect element that that generates a high MR ratio at a lower RA than a TMR element using a material of a conventional tunnel barrier layer or MgAl2O4. The magnetoresistance effect element includes a laminate in which an underlayer, a first ferromagnetic metal layer, a tunnel harrier layer, and a second ferromagnetic metal layer are laminated in that order, wherein the underlayer is made of TiN, NbN, TaN, ZrN or mixed crystals thereof, and the tunnel barrier layer is made of a compound that has a spinel structure and expressed by composition formula (1) below: (1) AxIn2Oy, where A is the non-magnetic divalent cation and represents cations of one or more elements selected from the group consisting of magnesium and zinc, x represents a number satisfying 0<x?2, and y represents a number satisfying 0<y?4.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 20, 2019
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 10388604
    Abstract: The inventive concepts relate to a semiconductor device including a field effect transistor and a method for manufacturing the same. The semiconductor device includes a substrate including first and second source/drain regions formed thereon, a gate electrode intersecting the substrate between the first and second source/drain regions, and an active contact electrically connecting the first and second source/drain regions to each other. The active contact is spaced apart from the gate electrode. The active contact includes first sub-contacts provided on the first and second source/drain regions so as to be connected to the first and second source/drain regions, respectively, a second sub-contact provided on the first sub-contacts to electrically connect the first sub-contacts to each other, and a barrier layer provided between the second sub-contact and each of the first sub-contacts.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changseop Yoon, Hyung Jong Lee, Boram Im
  • Patent number: 10388799
    Abstract: Stable electric characteristics and high reliability are provided to a miniaturized and integrated semiconductor device including an oxide semiconductor. In a transistor (a semiconductor device) including an oxide semiconductor film, the oxide semiconductor film is provided along a trench (groove) formed in an insulating layer. The trench includes a lower end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the lower end corner portion.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Toshinari Sasaki
  • Patent number: 10379396
    Abstract: The present disclosure discloses a display panel and a display device. The display panel includes an array substrate and an opposite substrate arranged opposite to each other; the array substrate includes a box alignment area facing the opposite substrate, a circuit test area located on a side of the box alignment area; the opposite substrate includes a base substrate, a conductive black matrix arranged on a side of the base substrate facing the array substrate; the display panel further includes an electrostatic discharging layer electrically connected respectively with the conductive black matrix and a GND wire in the circuit test area; the conductive black matrix is provided with a thickened area in at least an area in contact with the electrostatic discharging layer; a thickness of the thickened area of the conductive black matrix is more than a thickness of other areas of the conductive black matrix.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 13, 2019
    Assignees: BOE Technology Group Co, Ltd., Ordos Yuansheng Optoelectronics Co, Ltd.
    Inventors: Yanyan Zhao, Jingyi Xu, Fuqiang Tang, Yanwei Ren, Kunpeng Zhang, Yu Liu, Yuelin Wang
  • Patent number: 10381353
    Abstract: A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10?4 ?cm to 1.0×104 ?cm or a sheet resistance in a range from 1.0×102?/? to 1.0×1010?/?.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 13, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jenn-Gwo Hwu, Samuel C. Pan, Chien-Shun Liao, Kuan-Hao Tseng