Patents Examined by Julia Slutsker
  • Patent number: 12295162
    Abstract: An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are made of materials respectively represented by chemical formulas of AlxGa(1-x)N, AlyGa(1-y)N, and AlzGa(1-z)N. For each of the p-i-n heterojunction stacks, x decreases and z increases along a direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: May 6, 2025
    Assignee: HUNAN SAN'AN SEMICONDUCTOR CO., LTD.
    Inventors: Boting Liu, Yutao Fang, Shuai Chen, Nientze Yeh, Fuchin Chang
  • Patent number: 12295239
    Abstract: The invention provides a flexible display panel and a flexible display device. The flexible display panel includes: a substrate, an auxiliary cathode provided on the substrate, an separation layer disposed on the substrate and the auxiliary cathode and defining a first opening to expose the auxiliary cathode, a passivation layer disposed on the separation layer and extending into the first opening as an undercut structure, an auxiliary anode arranged in the first opening and connected to the auxiliary cathode, and a cathode layer arranged on the auxiliary anode with a left end and a right end respectively connected with the auxiliary anode.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: May 6, 2025
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Shijian Qin, Wanliang Zhou
  • Patent number: 12288820
    Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.
    Type: Grant
    Filed: November 15, 2023
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chang Sun, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, TsuChing Yang, Feng-Cheng Yang, Chung-Te Lin
  • Patent number: 12278102
    Abstract: A semiconductor device includes a substrate, a semiconductor stacking portion formed on the substrate, a silicon nitride passivation film covering the surface of the semiconductor stacking portion, and oxygen atoms existing at an interface between the silicon nitride passivation film and the semiconductor stacking portion. The semiconductor stacking portion includes a plurality of nitride semiconductor layers. The interfacial oxygen content at the passivation film and stacking portion interface is 0.6×1015 oxygen atoms/cm2 or less.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: April 15, 2025
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kazuhide Sumiyoshi, Masaya Okada, Kazutaka Inoue, Takumi Yonemura
  • Patent number: 12272767
    Abstract: An embodiment discloses an ultraviolet light emitting element including: a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, and an etched region in which the first conductive semiconductor layer is exposed; a first insulating layer disposed on the light emitting structure and including a first hole which exposes a portion of the etched region; a first electrode electrically connected to the first conductive semiconductor layer; and a second electrode electrically connected to the second conductive semiconductor layer, wherein the light emitting structure includes an intermediate layer regrown on the first conductive semiconductor layer exposed in the first hole, the first electrode is disposed on the intermediate layer, the etched region includes a first etched region disposed at an inner side and a second etched region disp
    Type: Grant
    Filed: May 11, 2023
    Date of Patent: April 8, 2025
    Assignee: Photon Wave Co., Ltd.
    Inventors: Youn Joon Sung, Seung Kyu Oh, Jae Bong So, Gil Jun Lee, Won Ho Kim, Tae Wan Kwon, Eric Oh, Il Gyun Choi, Jin Young Jung
  • Patent number: 12266720
    Abstract: Transistor structures with monocrystalline metal chalcogenide channel materials are formed from a plurality of template regions patterned over a substrate. A crystal of metal chalcogenide may be preferentially grown from a template region and the metal chalcogenide crystals then patterned into the channel region of a transistor. The template regions may be formed by nanometer-dimensioned patterning of a metal precursor, a growth promoter, a growth inhibitor, or a defected region. A metal precursor may be a metal oxide suitable, which is chalcogenated when exposed to a chalcogen precursor at elevated temperature, for example in a chemical vapor deposition process.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: April 1, 2025
    Assignee: Intel Corporation
    Inventors: Carl Naylor, Chelsey Dorow, Kevin O'Brien, Sudarat Lee, Kirby Maxey, Ashish Verma Penumatcha, Tanay Gosavi, Patrick Theofanis, Chia-Ching Lin, Uygar Avci, Matthew Metz, Shriram Shivaraman
  • Patent number: 12262537
    Abstract: A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer.
    Type: Grant
    Filed: January 23, 2024
    Date of Patent: March 25, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Taek Jung, Joong-Shik Shin, Byung-Kwan You
  • Patent number: 12255065
    Abstract: A method of manufacturing a semiconductor device includes: forming electrode holes by etching a mold structure including a mold layer and a support layer which are stacked on a substrate; forming lower electrode pillars filling the electrode holes; etching a portion of the support layer between the lower electrode pillars to form a support pattern having a through-hole exposing a portion of a top surface of the mold layer; removing the mold layer through the through-hole to expose sidewalls of the lower electrode pillars; and selectively forming lower electrode patterns on the sidewalls and top surfaces of the lower electrode pillars.
    Type: Grant
    Filed: December 5, 2023
    Date of Patent: March 18, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Suk Lee, Jungoo Kang, Gihee Cho, Sanghyuck Ahn
  • Patent number: 12256553
    Abstract: Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: March 18, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Jeffery Brandt Hull, Anish A. Khandekar, Hung-Wei Liu, Sameer Chhajed
  • Patent number: 12243890
    Abstract: A semiconductor device structure for sensing an incident light includes a substrate, a passivation layer and a wiring structure. The substrate has a device embedded therein. The passivation layer is disposed on the substrate, where the passivation layer has a first side and a second side opposite to the first side, the first side of the passivation layer includes microstructures disposed on the substrate, and the second side of the passivation layer is a continuous flat plane, wherein each of the microstructures has a cross-section in a shape of a triangle, trapezoid or arc. The wiring structure is disposed on the substrate, where the writing structure includes at least one contact and metal interconnection patterns respectively formed in different dielectric layers, and the at least one contact and the metal interconnection patterns are electrically connected, where the substrate is located between the passivation layer and the wiring structure.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Ping Pan, Hung-Jen Hsu
  • Patent number: 12243932
    Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack of the NCFET and FE-FET devices includes a non-ferroelectric interfacial layer formed over the semiconductor channel, and a ferroelectric gate dielectric layer formed over the interfacial layer. The ferroelectric gate dielectric layer is formed by inserting dopant-source layers in between amorphous high-k dielectric layers and then converting the alternating sequence of dielectric layers to a ferroelectric gate dielectric layer by a post-deposition anneal (PDA). The ferroelectric gate dielectric layer has adjustable ferroelectric properties that may be varied by altering the precisely-controlled locations of the dopant-source layers using ALD/PEALD techniques. Accordingly, the methods described herein enable fabrication of stable NCFET and FE-FET FinFET devices that exhibit steep subthreshold slopes.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Yang Lai, Chun-Yen Peng, Sai-Hooi Yeong, Chi On Chui
  • Patent number: 12237342
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.
    Type: Grant
    Filed: November 15, 2023
    Date of Patent: February 25, 2025
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Masayoshi Fuchi
  • Patent number: 12232320
    Abstract: A memory device includes a substrate, a stack over the substrate, and a gate line slit extending along a first direction and dividing the stack into two portions. The stack includes a connection portion that connects the two portions of the stack. The connection portion includes at least two sub-connection portions along a second direction perpendicular to the first direction. The gate line slit includes at least two portions along the first direction. Each sub-connection portion is between adjacent two portions of the gate line slit.
    Type: Grant
    Filed: August 22, 2023
    Date of Patent: February 18, 2025
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Qiang Xu, Fandong Liu, Zongliang Huo, Zhiliang Xia, Yaohua Yang, Peizhen Hong, Wenyu Hua, Jia He
  • Patent number: 12224174
    Abstract: A method of manufacturing a stacked structure includes forming a first metal buffer layer including crystal grains on a base substrate, forming a second metal buffer material layer on the first metal buffer layer, and crystallizing the second metal buffer material layer to form a second metal buffer layer, wherein the second metal buffer material layer includes crystal grains, and a density of the crystal grains of the second metal buffer material layer is lower than a density of the crystal grains of the first metal buffer layer.
    Type: Grant
    Filed: November 6, 2023
    Date of Patent: February 11, 2025
    Assignees: SAMSUNG DISPLAY CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Mann Ho Cho, Kwang Sik Jeong, Hyeon Sik Kim, Hyun Eok Shin, Byung Soo So, Ju Hyun Lee
  • Patent number: 12224355
    Abstract: A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit.
    Type: Grant
    Filed: November 8, 2023
    Date of Patent: February 11, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Jun Koyama
  • Patent number: 12224339
    Abstract: An HEMT includes an aluminum gallium nitride layer. A gallium nitride layer is disposed below the aluminum gallium nitride layer. A zinc oxide layer is disposed under the gallium nitride layer. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer and between the drain electrode and the source electrode.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: February 11, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 12218201
    Abstract: A semiconductor structure, including: a base substrate; an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, and/or silicon germanium, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising: a first plurality of volumes of semiconductor material having a tensile strain of at least about 0.6%; and a second plurality of volumes of semiconductor material having a compressive strain of at least about ?0.6%. Also described is a method of preparing a semiconductor structure and a segmented strained silicon-on-insulator device.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: February 4, 2025
    Assignees: National University of Singapore, Soitec
    Inventors: Bich-Yen Nguyen, Christophe Maleville, Walter Schwarzenbach, Gong Xiao, Aaron Thean, Chen Sun, Haiwen Xu
  • Patent number: 12218217
    Abstract: A layer structure including a dielectric layer, a method of manufacturing the layer structure, and an electronic device including the layer structure are disclosed. The layer structure including a lower layer, a dielectric layer, and an upper layer sequentially stacked. The dielectric layer includes sequentially stacked first, second, and third layers, wherein one of the first layer or the third layer is a ferroelectric, the other one is an anti-ferroelectric, and the second layer is an oxide layer. In one example, the dielectric layer may further include a fourth layer on the third layer.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: February 4, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yunseong Lee, Jinseong Heo, Taehwan Moon, Seunggeol Nam, Dukhyun Choe
  • Patent number: 12211744
    Abstract: A method of forming nanocrystalline graphene according to an embodiment may include: arranging a substrate having a pattern in a reaction chamber; injecting a reaction gas into the reaction chamber, where the reaction gas includes a carbon source gas, an inert gas, and a hydrogen gas that are mixed; generating a plasma of the reaction gas in the reaction chamber; and directly growing the nanocrystalline graphene on a surface of the pattern using the plasma of the reaction gas at a process temperature. The pattern may include a first material and the substrate may include a second material different from the first material.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: January 28, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keunwook Shin, Hyeonjin Shin, Alum Jung, Changseok Lee
  • Patent number: 12211926
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kong-Beng Thei, Chien-Chih Chou, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky