Abstract: A device module includes first and second conductive layers, and first and second functional layers between the first and second conductive layers. The first functional layer includes a plurality of capacitors and a plurality of via electrodes isolated from the plurality of capacitors. A plurality of inductors are formed in the second functional layer, each arranged along a thickness direction of the second functional layer. Thus, a first terminal of the inductor is electrically coupled with the first conductive layer through corresponding one of the via electrodes, and a second terminal of the inductor is electrically coupled with the second conductive layer. The device module simplifies the layout and wiring of a multi-phase circuit by directly installing the driver on the multi-inductor array with the pins being arranged longitudinally, and improves the effective utilization of inductor and capacitor materials.

Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a first silicon oxide layer contacting the semiconductor fin at a first interface and including nitrogen at a first concentration. The semiconductor device includes a second silicon oxide layer contacting the first silicon oxide layer at a second interface and including nitrogen at a second concentration that is greater than the first concentration. And the semiconductor device further includes a gate electrode over the second silicon oxide layer.

Abstract: A semiconductor device comprising: a plurality of semiconductor chips; a first conductor and a second conductor arranged at opposite sides of the semiconductor chips, wherein the second conductor comprises a plurality of pillars, and wherein each of the semiconductor chips comprises: a first surface facing the first conductor; a first electrode arranged on the first surface and electrically coupled to the first conductor; a second surface opposite to the first surface; a second electrode arranged on the second surface and electrically coupled to a respective one of the pillars, and a control electrode arranged on the second surface and configured to switch a current flowing between the first electrode and the second electrode; a circuit board comprising openings penetrated by the plurality of pillars, wherein the circuit board further comprises an electrically insulating layer, a first conductive film and a second conductive film.

Abstract: A display device, according to the present invention, comprises: semiconductor light-emitting devices; and a substrate on which the semiconductor light-emitting devices are received, and which comprises wiring electrodes electrically connected to the semiconductor light-emitting devices. The substrate comprises: a base part; assembly electrodes disposed on the base part so as to extend in one direction; a dielectric layer formed so as to cover the assembly electrodes; and a partition part formed on the dielectric layer and forming cells in which the semiconductor light-emitting devices are seated, wherein the partition part comprises a first partition part formed from metal material, and a second partition part formed from insulating material, and the first partition part and second partition part comprise a micropattern.

Abstract: An integrated package and a method for making the same are provided. The integrated package includes: a first substrate including: a first interconnection area having a plurality of first interconnection structures; and a first alignment structure disposed outside the first interconnection area; a second substrate stacked above the first substrate and including: a second interconnection area having a plurality of second interconnection structures; and a second alignment structure disposed outside the second interconnection area, wherein the second alignment structure is substantially aligned with the first alignment structure in a stacking direction of the first substrate and the second substrate; and a connecting element disposed between the first substrate and the second substrate and configured for electrically connecting at least one of the plurality of first interconnection structures with at least one of the plurality of second interconnection structures.

Abstract: A semiconductor structure includes a first nanosheet field-effect transistor device having a plurality of first nanosheet channel layers disposed on a substrate, a second nanosheet field-effect transistor device adjacent the first field-effect transistor nanosheet device, the second field-effect transistor nanosheet device having a plurality of second nanosheet channel layers disposed on the substrate, a first source/drain region disposed between opposing sidewalls of the plurality of first nanosheet channel layers and the plurality of second nanosheet channel layers and extending into the substrate, and source/drain sidewall spacers disposed on sidewalls of the first source/drain region extending into the substrate.

Abstract: Embodiments of the present disclosure include techniques related to techniques for processing materials for manufacture of group-III metal nitride and gallium based substrates. More specifically, embodiments of the disclosure include techniques for substrates with a controlled oxygen gradient using a combination of processing techniques. Merely by way of example, the disclosure can be applied to growing crystals of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, and others for manufacture of bulk or patterned substrates. Such bulk or patterned substrates can be used for a variety of applications including optoelectronic and electronic devices, lasers, light emitting diodes, solar cells, photo electrochemical water splitting and hydrogen generation, photodetectors, integrated circuits, and transistors, and others.

Abstract: An isolation structure of a semiconductor device includes a substrate, a first isolation structure and a second isolation structure. The substrate has a first region and a second region, and there is a boundary between the first region and the second region. The first isolation structure is disposed in the first region of the substrate, and the first isolation structure includes a dielectric liner and a first insulating layer. The second isolation structure is disposed in the second region of the substrate, and the second isolation structure includes a second insulating layer. The first isolation structure and the second isolation structure are respectively located on both sides of the boundary.

Abstract: Disclosed is a light-emitting device, a preparation method, and a display panel. The light-emitting device includes an anode layer and a cathode layer disposed opposite to each other, a light-emitting layer disposed between the anode layer and the cathode layer, and a first interface-modifying layer disposed between the light-emitting layer and the anode layer. The first interface-modifying layer includes a thiophene-based polymer and a graphyne doped in the thiophene-based polymer and includes a first sub-layer close to the light-emitting layer and a second sub-layer close to the anode layer, and a doping ratio of the graphyne in the first sub-layer is greater than a doping ratio of the graphyne in the second sub-layer.

Abstract: Provided is a method of manufacturing a Si—SiC-based composite structure capable of improving the manufacturing efficiency of the Si—SiC-based composite structure. The method of manufacturing a Si—SiC-based composite structure includes a step of impregnating a molten metal containing Si into a molded body containing SiC by heating a supply body containing Si under a state in which the supply body is in contact with the molded body, wherein a contact portion of the supply body with the molded body is a part of a surface of the supply body facing the molded body.

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a channel region of a semiconductor layer, a source/drain epitaxial layer is formed on opposing sides of the dummy gate structure, a planarization operation is performed on the source/drain epitaxial layer, the planarized source/drain epitaxial layer is patterned, the dummy gate structure is removed to form a gate space, and a metal gate structure is formed in the gate space.

Abstract: An insulation sheet for a display light source is provided. An insulation sheet for a display light source according to an embodiment of the present invention is provided on an opposite surface opposite to a circuit board mounting surface on which multiple LED elements configuring a light source of a display are mounted while being spaced a predetermined interval apart from each other, so as to block heat generated from the multiple LED elements from being transmitted in a direction perpendicular to the opposite surface. Accordingly, the insulation sheet can minimize vertical transfer of received heat as well as reducing the heating level of the multiple LED elements, and is thus advantageous in minimizing or preventing heat transfer in an undesirable direction and/or of an undesirable amount.

Abstract: The present application relates to an OLED light-emitting unit for use in a top-emission OLED substrate, which includes an anode, a cathode, and an organic functional layer arranged between the anode and the cathode. The anode includes a first metal layer and a second metal layer arranged in sequence, a separation layer is arranged between the first metal layer and the second metal layer, and a thickness of the second metal layer is within a preset threshold range such that metal atoms of the second metal layer are capable of being thermally agglomerated and rearranged under a preset condition to form a concave-convex structure on a surface of the second metal layer.

Abstract: A method for modifying an insulating film is provided. The method includes a first step of preparing an insulating film containing hydrogen, and a second step of performing microwave treatment on the insulating film to release the hydrogen in the insulating film as water molecules, so that a hydrogen concentration in the insulating film is reduced. Note that the microwave treatment is preferably performed using an oxygen gas and an argon gas at a temperature range of higher than or equal to 200° C. and lower than or equal to 300° C., and the proportion of the flow rate of the oxygen gas to the total of the flow rate of the oxygen gas and the flow rate of the argon gas is preferably greater than 0% and less than or equal to 50%.

Abstract: A process for manufacturing a silicon carbide semiconductor device includes providing a silicon carbide wafer, having a substrate. An epitaxial growth for formation of an epitaxial layer, having a top surface, is carried out on the substrate. Following upon the step of carrying out an epitaxial growth, the process includes the step of removing a surface portion of the epitaxial layer starting from the top surface so as to remove surface damages present at the top surface as a result of propagation of dislocations from the substrate during the previous epitaxial growth and so as to define a resulting top surface substantially free of defects.

Abstract: A processing system includes one or more processing chambers, and a system controller configured to cause the processing system to perform (a) a pre-clean process on exposed surfaces of a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region, (b) a first deposition process to form an amorphous silicon-containing layer on the exposed surfaces of the semiconductor structure, (c) a recrystallization anneal process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer within the trench, (d) an etch process to remove remaining portions of the amorphous silicon-containing layer, and (e) a second deposition process, to epitaxially form a source/drain region over the silicon-containing crystalline layer wi

Abstract: Proposed is a high voltage semiconductor device and a method of manufacturing the same and, more particularly, a high voltage semiconductor device and a method of manufacturing the same, which allow the upper end of an air gap or void formed in a DTI region to be positioned relatively deep in a substrate by forming a wide region with a relatively wide lateral width on the upper part of the DTI region, thereby preventing external exposure of the air gap in a subsequent process and preventing foreign substances such as tungsten from remaining on the upper side of the DTI region accordingly.

Abstract: A semiconductor device in which variation in characteristics is small is provided. A first insulator is formed; a first insulator is formed; a conductor is formed over the first insulator; a second insulator is formed over the conductor; a third insulator is formed over the second insulator; an oxide is formed over the third insulator; first heat treatment is performed; and second heat treatment following the first heat treatment is performed. The temperature of the first heat treatment is lower than the temperature of the second heat treatment.

Abstract: Active semiconductor devices in an integrated circuit are provided lateral electrical isolation by surrounding narrow deep trench isolation regions that are merged at shared portions of the narrow deep trench isolation regions. A wide deep trench isolation region laterally surrounds the merged narrow deep trench isolation regions.

Abstract: III-Nitrides epilayer(s) are grown “remotely” on a 2D material layer, such as graphene or h-BN, aBN, or polycrystalline BN coated crystalline substrate, where the Nitride-face surface of the epilayer faces the 2D material. A small mechanical force using a 2D material-based layer transfer process is used to separate the III-Nitrides epilayer(s) at their interface with the 2D material layer. Alternatively, the III-Nitrides epilayer is removed by mechanical force from a substrate with the assistance of a first thermal release tape and an optional metal layer on the epilayer and then a second thermal release tape and/or optional metal layer, is applied to the Nitride-face of the epilayer, the first thermal release tape and first metal layer are removed, the Ga-face surface is bonded to a substrate, and the second thermal release tape is removed. The resulting Nitride-face surface of the epilayer has high quality. A HEMT may be formed using the above structures.