Patents Examined by Julia Slutsker
  • Patent number: 11222903
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the method comprises: providing a substrate; forming an alternating stack over the substrate, the alternating stack comprising a plurality of tiers of sacrificial layer/insulating layer pairs extending along a first direction substantially parallel to a top surface of the substrate; forming a plurality of tiers of word lines extending along the first direction based on the alternating stack; forming at least one connection portion conductively connecting two or more of the word lines of the plurality of tiers of word lines; and forming at least one metal contact via conductively shared by connected word lines, the at least one metal contact via being connected to at least one metal interconnect.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: January 11, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Qiang Xu, Fandong Liu, Zongliang Huo, Zhiliang Xia, Yaohua Yang, Peizhen Hong, Wenyu Hua, Jia He
  • Patent number: 11222998
    Abstract: A light emitting apparatus includes: a package substrate that includes a recess that opens on a top surface of the package substrate; a light emitting device housed in the recess; a window member provided to cover an opening of the recess; and a metal bonding part that seals a space between the package substrate and the window member. The package substrate includes a packaging surface on which the light emitting device is mounted and a metal electrode is provided, an isolation surface provided in a shape of a frame on an outer side of the packaging surface, and a light reflection surface sloping from the isolation surface toward the top surface, and a metal layer is provided on the light reflection surface with a clearance from the isolation surface.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: January 11, 2022
    Assignee: NIKKISO CO., LTD.
    Inventors: Hiroyasu Ichinokura, Shoichi Niizeki
  • Patent number: 11217718
    Abstract: According to an embodiment of the present disclosure, a photodetector device can include a substrate layer; a bottom contacting layer disposed over a surface of the substrate layer and having a first contacting region and a second contacting region, the bottom contacting layer providing a low resistance path between the first and second contacting regions; an insulating layer disposed over a surface of the bottom contacting layer; an intrinsic region disposed within the insulating layer, the intrinsic region in electrical contact with the first contacting region of the bottom contacting layer, the intrinsic region comprising a low band-gap material; a metal contact disposed within the insulating layer and in electrical contact with the second contacting region of the bottom contacting layer; an anode in electrical contact with the intrinsic region; and a cathode in electrical contact with the metal contact.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: January 4, 2022
    Assignee: Allegro MicroSystems, LLC
    Inventors: Bryan Cadugan, Harianto Wong, William P. Taylor
  • Patent number: 11217493
    Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate; a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, wherein the second source/drain layer comprises a first semiconductor material which is stressed; and a gate stack surrounding a periphery of the channel layer.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: January 4, 2022
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 11211284
    Abstract: A semiconductor device includes a plurality of patterns defined between a plurality of trenches and disposed on a substrate. A leaning control layer is disposed on sidewalls and bottoms of the plurality of trenches. A gap-fill insulating layer is disposed on the leaning control layer. At least one of the plurality of trenches has a different depth from one of the plurality of trenches adjacent thereto.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: December 28, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Juyeon Kim, Hanmei Choi, Sukjin Chung, Bongjin Kuh, Changyong Kim, Hakyu Seong
  • Patent number: 11205656
    Abstract: The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: December 21, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Qiang Xu, Zhiliang Xia, Ping Yan, Guangji Li, Zongliang Huo
  • Patent number: 11205621
    Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: December 21, 2021
    Assignee: STMICROELECTRONICS, INC.
    Inventors: John H. Zhang, Walter Kleemeier, Paul Ferreira, Ronald K. Sampson
  • Patent number: 11196013
    Abstract: A flexible display panel and a display module are provided. The flexible display panel includes a bending section. At least one trace is defined with the bending section, and each trace includes at least one stress relief apparatus.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: December 7, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Liang Fang, Ding Ding
  • Patent number: 11189769
    Abstract: A light-emitting device is disclosed that includes a substrate; a semiconductor structure on the substrate, a wavelength conversion element on the substrate, opposite the semiconductor structure; an insulating side coating around the semiconductor structure; and a reflective side coating around the wavelength conversion element and the substrate, the reflective layer being stacked over the insulating side coating, the reflective side coating having a first surface that is over a second surface of the insulating side coating.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: November 30, 2021
    Assignee: LUMILEDS LLC
    Inventors: Ruen-Ching Law, Tze-Yang Hin
  • Patent number: 11183574
    Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Ziwei Fang, Chun-I Wu, Huang-Lin Chao
  • Patent number: 11183599
    Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng Chen, Szu-Wei Huang, Hung-Li Chiang, Cheng-Hsien Wu, Chih Chieh Yeh
  • Patent number: 11171219
    Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Yang Lai, Bo-Feng Young, Chun-Yen Peng, Sai-Hooi Yeong, Chi On Chui, Chih-Yu Chang
  • Patent number: 11152389
    Abstract: A method for reducing an epitaxial growth loading effect in a patterned device includes forming a first trench and a second trench in a substrate and in a first insulating layer over the substrate to form a low pattern density region and a high pattern density region. The first trench has a larger cross-sectional area than the second trench. The method further includes isolating the first trench from the second trench by using a first mask. The method further include disposing a second insulating layer in the first trench. The method further includes removing a portion of the first mask in order to expose the second trench. The method further includes growing an epitaxial layer in the second trench.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: October 19, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhen Fang, Haihui Huang, Er Jiang Xu, Meng Wang
  • Patent number: 11114618
    Abstract: In one embodiment, there is provided a method of manufacturing an organic layer. The method includes: forming an organic material solution layer on a substrate; and heating, by a directional heat source assembly, at least a first portion of organic material solution of the organic material solution layer that is inside a to-be-treated area of the substrate, to increase an evaporation rate of the first portion of the organic material solution, whereby, reducing a thickness difference, due to different evaporation rates of the first portion of the organic material solution and a second portion of the organic material solution of the organic material solution layer that is outside the to-be-treated area of the substrate, of the organic layer that is cured from the organic material solution layer.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: September 7, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yu Ai, Xuewu Xie, Yubao Kong, Shi Sun, Hao Liu, Ameng Zhang, Bowen Liu
  • Patent number: 11114569
    Abstract: The present application discloses a semiconductor device with an oxidized intervention layer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a memory unit including a memory unit conductive layer positioned above the substrate and a lateral oxidized intervention layer positioned below the memory unit conductive layer, and a control unit positioned in the substrate and below the lateral oxidized intervention layer. The lateral oxidized intervention layer includes a sidewall portion and a center portion, and the sidewall portion has a greater concentration of oxygen than the center portion.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: September 7, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Wei Huang
  • Patent number: 11114443
    Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example method may include patterning a working surface of a semiconductor wafer. The method may further include performing a vapor etch on a first dielectric material at the working surface to recess the first dielectric material to a first intended depth of an opening relative to the working surface and to expose a second dielectric material on a sidewall of the opening. The method may further include performing a wet etch on the second dielectric material to recess the second dielectric material to the intended depth.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Vivek Yadav, Fatma Arzum Simsek-Ege, Sanjeev Sapra, Thomas A. Figura, Kangle Li
  • Patent number: 11114484
    Abstract: A photoelectric conversion apparatus includes, a semiconductor substrate having a photoelectric conversion unit performing photoelectric conversion on entering light and accumulating first electric charges, a first transistor electrically connected to the photoelectric conversion unit and having a first gate on a second surface, and a second transistor having a second gate shorter than the first gate on the second surface, a first fixed charge film continuously provided directly or with an insulating film in between in an area overlapping the photoelectric conversion unit on a first surface and the second transistor, the first fixed charge film having fixed charges of the first polarity, and a second fixed charge film provided directly or with an insulating film in between in an area overlapping the second transistor and the first fixed charge film, the second fixed charge film having fixed charges of a second polarity.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 7, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takumi Ogino, Hideaki Ishino
  • Patent number: 11104997
    Abstract: Described herein is a technique capable of substantially cancelling out a machine difference of a pressure control valve. According to one aspect of the technique of the present disclosure, there is provided a substrate processing apparatus including: a sensor detecting a valve opening degree; a first control circuit outputting a valve opening degree control signal based on a valve opening degree value detected by the sensor and a deviation between a pressure of the process chamber and a target vacuum pressure value; a second control circuit outputting an electropneumatic control signal based on the valve opening degree control signal; and a span adjustment circuit adjusting the first or second control circuit so that an upper limit value of the valve opening degree is set to a predetermined full opening degree less than a physically defined full opening degree.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: August 31, 2021
    Assignee: Kokusai Electric Corporation
    Inventors: Naoya Miyashita, Tomoshi Taniyama
  • Patent number: 11094747
    Abstract: An organic EL display apparatus (100) has a plurality of pixels including red pixels (R), green pixels (G) and blue pixels (B), the apparatus (100) including: a substrate (1); a plurality of organic EL elements (10) supported on the substrate, with one organic EL element provided in each pixel; a generally lattice-shaped first bank (21) defining the pixels, the first bank including a plurality of first portions (21A) extending in a first direction and a plurality of second portions (21B) extending in a second direction that crosses the first direction; and a plurality of second banks (22) provided on a top portion (21t) of the first bank, wherein the second banks are not formed at intersections (cr) between the first portions and the second portions of the first bank, and the second banks are more liquid repellent than the first bank.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: August 17, 2021
    Assignee: Sakai Display Products Corporation
    Inventors: Yukiya Nishioka, Katsuhiko Kishimoto
  • Patent number: 11094761
    Abstract: An organic light emitting display device and a method of fabricating thereof are discussed. The organic light emitting display device according to an example of the invention comprises a first substrate; a plurality of first bank layers arranged along a first direction and a second direction on the first substrate to define a plurality of pixels; a plurality of second bank layers disposed along the first direction on the first bank layers to divide columns of pixels having different colors; a plurality of third bank layers disposed along the second direction on the first bank layers; and an organic light emitting diode in each pixel, the organic light emitting diode including an organic light emitting layer, wherein the third bank layer is made of a same material as the second bank layer and the width of the third bank layer is smaller than that of the second bank layer.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 17, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Sung-Soo Park, Nack-Youn Jung, Hee-Jin Kim, Hak-Min Lee, Myung-O Joo, Jeong-Mook Choi