Abstract: Another embodiment of the instant invention is a method of fabricating a conductive interconnect for providing an electrical connection between a first conductor and a second conductor for an electrical device formed in a semiconductor substrate, the method comprising the steps of: forming a dielectric layer (layer 226 of FIG. 2a) on the first conductor (conductor 222 of FIG. 2a), the dielectric layer having at least one opening which exposes the first conductor; forming a layer of an oxygen-sensitive material (layer 234 of FIG.

Abstract: A metal layer A constituting the stripe-shaped cathode electrode is formed on the surface of the organic electroluminescence layer 13, a peeling film B is stuck to the surface of the metal layer A through such an adhesive C as to reduce adhesion to the metal layer by the irradiation of ultraviolet light, and a pattern according to the stripe-shaped cathode electrodes 14 is baked onto the peeling film B by the irradiation of ultraviolet light E by using a mask D and the peeling film B is then peeled from the organic electroluminescence layer 13.

Abstract: An ion implantation system for producing silicon wafers having relatively low defect densities, e.g., below about 1×106/cm2, includes a fluid port in the ion implantation chamber for introducing a background gas into the chamber during the ion implantation process. The introduced gas, such as water vapor, reduces the defect density of the top silicon layer that is separated from the buried silicon dioxide layer.

Abstract: The instant invention is a method for fabricating a trench contact to a deep trench capacitor with a polysilicon filling in a trench hole formed in a silicon substrate. An epitaxy process is performed to selectively grow silicon above the polysilicon filling in the trench hole. An opening leading to the polysilicon filling is anisotropically etched into the epitaxially grown silicon. The opening has lateral dimensions that are smaller than those of the polysilicon filling, and the opening is filled with polysilicon.

Abstract: The present invention provides a process for fabricating a contact plug in a semiconductor substrate having a contact opening formed therein that comprises depositing a barrier layer in the contact opening and on at least a portion of the semiconductor substrate, depositing a contact metal on the barrier layer within the contact opening, removing a substantial portion of the contact metal and the barrier layer from the semiconductor substrate and forming a contact plug within the contact opening, and subjecting the contact plug to a temperature sufficient to anneal the barrier layer.

Abstract: A semiconductor manufacturing process wherein silicon nitride is plasma etched with selectivity to an overlying and/or underlying dielectric layer such as a silicon oxide or low-k material. The etchant gas includes a fluorocarbon reactant and an oxygen reactant, the ratio of the flow rate of the oxygen reactant to that of the fluorocarbon reactant being no greater than 1.5. The etch rate of the silicon nitride can be at least 5 times higher than that of the oxide. Using a combination of CH3F and O2 with optional carrier gasses such as Ar and/or N2, it is possible to obtain nitride:oxide etch rate selectivities of over 40:1. The process is useful for simultaneously removing silicon nitride in 0.25 micron and smaller contact or via openings and wide trenches in forming structures such as damascene and self-aligned structures.

Abstract: A silicon-on-insulator (SOI) device structure 100 formed using a self-aligned body tie (SABT) process. The SABT process connects the silicon body of a partially depleted (PD) structure to a bias terminal. In addition, the SABT process creates a self-aligned area of silicon around the edge of the active areas, as defined by the standard transistor active area mask, providing an area efficient device layout. By reducing the overall gate area, the speed and yield of the device may be increased. In addition, the process flow minimizes the sensitivity of critical device parameters due to misalignment and critical dimension control. The SABT process also suppresses the parasitic gate capacitance created with standard body tie techniques.