Abstract: To achieve promotion of stability of operational function of display device and enlargement of design margin in circuit design, in a display device including a pixel portion having a semiconductor element and a plurality of pixels provided with pixel electrodes connected to the semiconductor element on a substrate, the semiconductor element includes a photosensitive organic resin film as an interlayer insulating film, an inner wall face of a first opening portion provided at the photosensitive organic resin film is covered by a second insulating nitride film, a second opening portion provided at an inorganic insulating film is provided on an inner side of the first opening portion, the semiconductor and a wiring are connected through the first opening portion and the second opening portion and the pixel electrode is provided at a layer on a lower side of an activation layer.

Abstract: A memory element comprising first and second electrodes is provided. The first electrode is tapered such that a first end of the first electrode is larger than a second end of the first electrode. A resistance variable material layer is located between the first and second electrodes, and the second end of the first electrode is in contact with the resistance variable material. Methods for forming the memory element are also provided.

Abstract: A vertical conduction power electronic device package and corresponding assembly method comprising at least a metal frame suitable to house at least a plate or first semiconductor die having at least a first and a second conduction terminal on respective opposed sides of the first die. The first conduction terminal being in contact with said metal frame and comprising at least an intermediate frame arranged in contact with said second conduction terminal.

Abstract: After etching the interlayer dielectric film 4 formed on the lower layer interconnect line 1 into a shape with holes, the upper layer dielectric film 6 is etched into a shape with trenches utilizing the etching stopper 5. The etching stopper 5 which is exposed at the bottom of the trench is removed by additional etching, and then, the interlayer dielectric film 4 which is exposed at the bottom of the trench is etched back to a predetermined thickness. Subsequently, the hole and the trench are filled with an interconnect metal 10.

Abstract: Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.

Abstract: A semiconductor device having a semiconductor substrate, at least one of a protruding electrode and wiring formed on one surface of the semiconductor substrate, and a first resin film formed on this surface. The first resin film has elasticity low enough to reduce stress induced by a difference in thermal expansion coefficient between the semiconductor substrate and the first resin film. A second resin film, having higher elasticity or higher strength than the first resin film, may be formed on the other surface of the semiconductor substrate.

Abstract: A reciprocal design symmetry allows stacked wafers or die on wafer to use identical designs or designs that vary only by a few layers (e.g. metal interconnect layers). Flipping or rotating one die or wafer allows the stacked die to have a reciprocal orientation with respect to each other which may be used to decrease the interconnect required between the vertically stacked die and or wafers. Flipping and/or rotating may also be used to improve heat dissipation when wafer and/or die are stacked. The stacked wafers or die may then be packaged.

Abstract: The present invention discloses a semiconductor memory device having a bit line and a metal contact stud, wherein the metal contact stud is formed on a different layer from a layer on which the bit lines are formed.

Abstract: There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.

Abstract: In the semiconductor integrated circuit device, a first P+ type buried layer formed as an anode region and an N+ type diffused region formed in a cathode region are spaced from each other in the direction of the depth. This makes it possible to provide a semiconductor integrated circuit device in which a large depletion layer forming region can be provided in an N type region at a PN junction formed by first and second epitaxial layers and when a reverse bias voltage is applied to a diode element and in which a withstand voltage can be maintained by a depletion layer thus formed to prevent breakdown of elements in the device attributable to a breakdown current.

Abstract: A trench MOS-gated device having an upper surface includes a substrate having an upper layer of doped monocrystalline semiconductor material of a first conduction type. A gate trench in the upper layer has sidewalls and a floor lined with a first dielectric material and a centrally disposed core that is formed of a second dielectric material and extends upwardly from the first dielectric material on the trench floor to contact an interlevel dielectric layer overlying the gate trench. The remainder of the trench is substantially filled with a conductive material that encompasses and contacts the core of second dielectric material. A doped well region of a second conduction type overlies a drain zone of the first conduction type in the upper layer, and a heavily doped source region of the first conduction type contiguous to the gate trench and a heavily doped body region of the second conduction type are disposed in the well region at the upper surface.

Abstract: A process for manufacturing a programmable non-volatile memory device having floating-gate MOS transistors, and first and second MOSFETs, the second MOSFETs capable of sustaining gate voltages higher than the first MOSFETs, by forming a first gate oxide layer for the floating-gate MOS transistors, a second gate oxide layer for the first MOSFETs, and a third gate oxide layer for the second MOSFETs. The process includes: forming a first oxide layer over a substrate; selectively removing the first oxide layer from surface regions over the first MOSFETs, but not from surface regions over the floating-gate MOS transistors or the second MOSFETs; forming a second oxide layer over the first oxide layer and the regions over the first MOSFETs; removing the first and second oxide layer from a tunnel oxide region of the floating-gate MOS transistors; and forming a tunnel oxide layer over the second oxide layer and tunnel region oxide layer.