Abstract: A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.

Abstract: A light-emitting element includes a semiconductor laminated structure including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type different from the first conductivity type and an active layer sandwiched by the first and second semiconductor layers, a first electrode on one surface side of the semiconductor laminated structure, a conductive reflective layer on an other surface side of the semiconductor laminated structure for reflecting light emitted from the active layer, a contact portion partially formed between the semiconductor laminated structure and the conductive reflective layer and being in ohmic contact with the semiconductor laminated structure, and a second electrode on a part of a surface of the conductive reflective layer on the semiconductor laminated structure without contacting the semiconductor laminated structure for feeding current to the contact portion.

Abstract: A multicolor CMOS pixel sensor formed in a p-type semiconductor region includes a first detector formed from an n-type region of semiconductor material located near the surface of the p-type region. A first pinned p-type region is formed at the surface of the p-type region over the first detector, and has a surface portion extending past an edge of the pinned p-type region. A second detector is formed from an n-type region located in the p-type semiconductor region below the first detector. A second-detector n-type deep contact plug is in contact with the second detector and extends to the surface of the p-type semiconductor region. A second pinned p-type region is formed at the surface of the p-type semiconductor region over the top of the second-detector n-type deep contact plug. A surface portion of the second-detector deep contact plug extends past an edge of the second pinned p-type region.

Abstract: An optical cell for spectral analysis is disclosed generally comprising a monolithic cell body that transmits light, the cell body having an outer surface and a fluid channel for receiving a sample that defines an inner surface. The inner surface of said cell body includes a planar section, and the outer surface of said cell body likewise includes a planar section, which is adjacent and substantially parallel to the planar section of the inner surface. In certain embodiments, the ends of the channel are frustoconical, and ferrules are employed to secure sample inlet/outlet tubes to the cell.

Abstract: In some embodiments a method of forming a gold-aluminum electrical interconnect is described. The method may include interposing a diffusion retardant layer between the gold and the aluminum (1002), the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material; bringing into contact the diffusion retardant layer, the gold, and the aluminum (1004); forming alloys of gold and the diffusion retardant material in regions containing the material (1006) and forming gold-aluminum intermetallic compounds in regions substantially devoid of the material (1008); and forming a continuous electrically conducting path between the aluminum and the gold (1010). In some embodiments, a structure useful in a gold-aluminum interconnect is provided.

Abstract: A method of connecting a chip to a package in a semiconductor device includes printing an encapsulant to a predetermined thickness on at least a portion of the chip and package and printing a layer of conductive material on the encapsulant in a predetermined pattern between the chip and package. The printed conductive material conforms to an upper surface of the encapsulant such that the encapsulant defines a distance from the printed conductive material to the chip and package. The method further includes printing a second layer of encapsulant over the printed conductive material curing at least the second layer of encapsulant.

Abstract: A transistor outline package having a feedthrough via and lead configuration that maximizes the amount of usable area on a header of the package is disclosed. In one embodiment, the package includes a header having an interior surface that includes a first and second lead assembly. The first lead assembly includes two vias having a first diameter, with each first via being positioned along a first pin circle imaginarily defined on the interior surface of the header. Each first via also includes first leads received therein. The second lead assembly includes four vias having a second diameter each, with each second via being positioned along a second pin circle that has a diameter greater than that of the first pin circle. Each second via includes second leads received therein. This configuration increases usable area on the header interior surface between the leads, enabling relatively larger submounts to be placed thereon.

Abstract: An electronic device can include a first die having a first terminal at a first front side, and a second die having a second terminal at a second front side and a through via. In one aspect, a process of forming the electronic device includes supplying a second substrate including a die location of the second die. The process can also include attaching the second substrate to a handling substrate and singulating the second die from the second substrate before removing the handling substrate. In another aspect, the handling substrate can include a rigid substrate. The process can include orienting the front side of the first die and a back side of the second substrate front-to-back with respect to each other. In yet another aspect, the first terminal is electrically connected to the through via and the second terminal. In one embodiment, the electronic device can include a third die.

Abstract: An integrated circuit package system is provided in which an interposer of predetermined thickness including a central cavity is formed. Additionally, one or more contacts are formed around the central cavity on the interposer. The interposer is employed for connecting first and second packages.

Abstract: A semiconductor device includes a module board mounting thereon an electric component and including a plug at an edge of the module board, and a mount board including thereon a socket adapted to said plug on a surface portion of the mount board for mounting thereon the module board via said plug, wherein the mount board includes therein a heat radiation layer in contact with a bottom surface of the socket, wherein the socket comprises a heat radiation guide plate in contact with a side surface of the socket.

Abstract: A semiconductor package has a first substrate having a plurality of electrically conductive patterns formed thereon. A first semiconductor die is coupled to the plurality of conductive patterns. A second semiconductor die is coupled to the first semiconductor die by a die attach material. A third semiconductor die is coupled to the second semiconductor die by a die attach material. A second substrate having a plurality of electrically conductive patterns formed thereon is coupled to the third semiconductor die. A plurality of contacts is coupled to a bottom surface of the first substrate. A connector jack is coupled to the second substrate. A plurality of leads is coupled to the second semiconductor die by conductive wires.

Abstract: An IC which includes a first circuit and a plurality of first paired terminals each including a first power supply terminal and a first GND terminal which are connected to the first circuit, and a second circuit and a plurality of second paired terminals each including a second power supply terminal and a second GND terminal which are connected to the second circuit. The first and second paired terminals are isolated inside. A printed board with the IC mounted has an inductor which is provided in a route that guides a wiring line from the first GND terminal to the second GND terminal and the GND of the printed board. The printed board has a portion where each of the first GND terminals is arranged inside the terminal array of the IC. The inductor suppresses a high-frequency potential variation generated by the operation of the first circuit.

Abstract: An integrated circuit package system comprising: forming leads adjacent a die paddle having a die pad extension; forming a region having one of the leads depopulated for the die pad extension; and connecting an integrated circuit die to the die pad extension.

Abstract: An inductive device including an inductor coil located over a substrate, at least one electrically insulating layer interposing the inductor coil and the substrate, and a plurality of current interrupters each extending into the substrate, wherein a first aggregate outer boundary of the plurality of current interrupters substantially encompasses a second aggregate outer boundary of the inductor coil.

Abstract: A partly finished product of a semiconductor device includes a resin body encapsulating a semiconductor chip, first and second leads extended outwardly from the resin body, a dam bar connected between said first and second leads, and an excess resin portion protruding from the resin body between the first and second leads and the dam bar. The excess resin portion is cut off at two limited portions, and thereby two groove portions are formed in the excess resin portion. An apparatus for cutting the dam bar includes a punch having a cutting edge for cutting connection portions between the first and second leads and the dam bar and for cutting off the two limited portions of the excess resin portion. Since the cut region of the excess resin portion becomes smaller, a stress imparted to the resin body and/or the semiconductor chip through the excess resin portion can be smaller.

Abstract: A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.

Abstract: One embodiment of a microelectronic component system includes a base adapted for supporting a microelectronic component, a membrane sealed to the base, and a glass lid built-up on the membrane and hermetically sealing the membrane.

Abstract: A microelectronic connection component includes a substrate having a first surface, a second surface and a peripheral edge. First and second terminals are exposed at the first surface of the substrate. Wire bond pads are exposed proximate the peripheral edge of the substrate at the first surface. First conductive paths couple the first terminals to the wire bond pads. Bonding leads extend beyond the peripheral edge of the substrate. Second conductive paths couple the second terminals to the bonding leads.

Abstract: An electro-acoustic sensing device including a sensing chip, a carrier chip and a sealing element is provided. The sensing chip is for electro-acoustic transuding and thereby outputting an electrical signal. The carrier chip disposed below the sensing chip has at least one second connecting point, at least one electrical channel and at least one channel connecting point. The second connecting point is electrically contacted with the first connecting point. The second connecting point and the channel connecting point are located at different surfaces of the carrier chip. The electrical channel passes through the carrier chip and electrically connects the second connecting point and the channel connecting point. The electrical signal is transmitted to the channel connecting point via the first and the second connecting points and the electrical channel. The sealing element is disposed between the sensing chip and the carrier chip for air-tight coupling the two chips.

Abstract: There is provided a wiring substrate for connecting a mounting board on one surface thereof and mounting an integrated circuit chip on the opposite surface to the surface. The wiring substrate has a conductive connecting portion penetrating the substrate for connecting to at least a portion of a wiring layer of the integrated circuit chip, with the portion of a wiring layer formed on the substrate, and an insulating portion formed at a lateral side of the connecting portion for surrounding the connecting portion via a portion of the wiring substrate.