Abstract: Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like.

Abstract: A memory system includes an error correction code (“ECC”) generation circuit using write data to generate an ECC to be stored together with the write data; a memory device, during a write operation, storing received data and a received ECC in a memory core, and, during a read operation, checking for an error in data read from the memory core, correcting the error in read data using the ECC and outputting error-corrected data and the ECC, when the error in the read data is between one bit and N bits inclusive, and outputting the read data and the ECC when no error is present in the read data or the error in the read data exceeds N bits; and an error correction circuit correcting, when an error is present in data outputted from the memory device, the error in the data outputted using an ECC outputted from the memory device.

Abstract: The present invention relates to a method for transmission of a data packet in a cellular network between a transmitting node and a receiving node, the receiving node being configured to receive data packets from the transmitting node, the transmitting node supporting at least one frequency band composed of a plurality of carriers, the method comprising for the transmitting node the step of transmitting to the receiving node a plurality of data transmissions of the data packet according to a predetermined redundancy level, whereby the first of the plurality of data transmissions is transmitted in a resource area addressed by a scheduling occurrence, and the rest of the plurality of data transmissions are transmitted in the same resource area as the first data transmission, and each data transmission is transmitted on a different carrier.

Abstract: An error correcting system is provided. The error correcting system includes an error correcting code (ECC) circuit and a control circuit. The ECC circuit is configured to encode input data received from M input terminals to generate encoded data in response to a write operation, and output the encoded data. The input data includes write data associated with the write operation, and the encoded data includes the input data and associated parity data. The control circuit is coupled to at least one of the M input terminals. When the write operation is directed to a memory device having a data bit width less than M bits, the write data is inputted to a portion of the M input terminals, the control circuit is configured to provide reference data to another portion of the M input terminals, and the write data and the reference data serve as the input data.

Abstract: Provided herein may be a memory device, a memory system having the memory device, and a method of operating the memory device. The memory device may include a memory cell array configured to store data, a peripheral circuit configured to perform a program operation on the memory cell array, and a control logic configured to perform the program operation by controlling the peripheral circuit and to perform a status check operation after the program operation. Here, the control logic may be configured to, based on a determination that the status check operation has passed, perform a number-of-program pulses comparison operation by comparing a number of program pulses used in the program operation to a first preset range.

Abstract: A wireless device may decode a polar coded codeword using a successive cancellation list (SCL) decoder. The decoder may implement a distributed feedback architecture, where the decoder stores one or more state maps and a set of bit arrays in memory for each layer of decoding. For different phases of decoding in a layer, the decoder may update the state maps and sets of bit arrays to limit the resources used. Additionally, when performing bit updating following the decoding of a bit of the codeword, the decoder may not update each layer of the decoding process. Instead, each sub-decoder may send a state map up to the calling layer for bit updating when the sub-decoder has completed its invocation, and may not return any intermediate state maps prior to completing invocation. Thus, each decoder and sub-decoder may perform bit updating just twice, reducing the complexity and latency of decoding.

Abstract: A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.

Abstract: A circuit includes a memory configured to store a data unit and parity bits, the parity bits being based on a write address associated with the stored data unit. An address port is configured to receive a read address for the stored data unit. A decoding circuit is configured to generate a decoded write address from the read address and the parity bits, and an error detecting circuit is configured to determine if an address error exists based on a comparison of the decoded write address to the read address.

Abstract: A method for decoding a (n, k, d) cyclic code is disclosed. The method includes: receiving a word corresponding to the cyclic code; constructing a look-up table, wherein the look-up table includes k syndrome vectors and k error patterns; computing a syndrome vector of the received word by a hardware processor; comparing the weight of the syndrome vector of the received word with an error-correcting capacity; decoding the received word by adding the received word and the syndrome vector if the weight of the syndrome vector of the received word is not more than the error-correcting capacity; decoding the received word by inverting bits in the message section in sequence and re-compute a syndrome vector of the inverted received word if the weight of the syndrome vector of the received word is more than the error-correcting capacity.

Abstract: An error correction code (ECC) encoder includes a plurality of exclusive OR (XOR) gates configured to receive a “k”-bit original data in parallel and configured to perform a plurality of XOR operations to the “k”-bit original data to output a “(n?k)”-bit parity data. The “k”-bit original data and the “(n?k)”-bit parity data form an “n”-bit codeword, “k” denotes a natural number and “n” denotes a natural number which is greater than “k”.

Abstract: A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data set, then error correction may be performed on a copy of the entry to identify the correct physical address where the requested data set is stored. A copy of the requested data set may then be retrieved and sent to the host.

Abstract: A system and method for distributing data over a plurality of remote storage nodes. Data are split into segments and each segment is encoded into a number of codeword chunks. None of the codeword chunks contains any of the segments. Each codeword chunk is packaged with at least one encoding parameter and identifier, and metadata are generated for at least one file and for related segments of the at least one file. The metadata contains information to reconstruct from the segments, and information for reconstructing from corresponding packages. Further, metadata are encoded into package(s), and correspond to a respective security level and a protection against storage node failure. A plurality of packages are assigned to remote storage nodes to optimize workload distribution. Each package is transmitted to at least one respective storage node as a function iteratively accessing and retrieving the packages of metadata and file data.

Abstract: Provided are a base station apparatus, a terminal apparatus and a communication method, capable of an efficient retransmission control of uplink data of which a resource for transmission is not discerned in grant-free multiple access. A terminal apparatus configured to communicate with a base station apparatus includes a transmitter configured to transmit an identifying signal indicating that the terminal apparatus itself transmits an uplink data channel and the uplink data channel. The uplink data channel includes an uplink data bit, a bit representing an identifier of the terminal apparatus, a first error detection bit generated from the uplink data bit, and a second error detection bit generated from the identifier of the terminal apparatus. The first error detection bit is scrambled using the identifier of the terminal apparatus, and the second error detection bit is scrambled using the identifying signal.

Abstract: The application discloses video data redundancy control methods and apparatuses. Video packet redundancy control information is determined according to packet loss at a reception apparatus. The video packet redundancy control information is received from the reception apparatus. Video data is encoded according to the video packet redundancy control information to obtain encoded video data of a plurality of frames by a transmission apparatus. A frame-level redundancy budget is allocated for one of the plurality of frames according to the video packet redundancy control information. Further, the one of the plurality of frames is packetized according to the frame-level redundancy budget to generate a packetized frame. Redundancy coding is performed on the packetized frame to generate video packets including data packets and redundant packets for transmission to the reception apparatus.

Abstract: An example apparatus for error correction can include an array of memory cells and a controller. The controller can be configured to perform a dummy read on a portion of data stored in the array. The dummy read can include sending a portion of data on output buffers to a host. The controller can be configured to error correct the portion of data in the host. The controller can be configured to write the portion of data back to the array.

Abstract: A storage system and method for handling a burst of errors is provided. In one embodiment, the method comprises generating a protograph using an error code generation method; generating a first partially-lifted protograph based on the generated protograph that avoids a first burst of errors; generating a fully-lifted protograph based on the generated protograph and the generated first partially-lifted protograph; and providing the fully-lifted protograph to a storage system comprising a memory.

Abstract: An object of the present invention is to provide a highly-reliable content addressable memory. Provided is a content addressable memory including: a plurality of CAM cells; a word line joined to the CAM cells; a plurality of bit lines joined to the CAM cells; a plurality of search lines joined to the CAM cells; a match line joined to the CAM cells; a match amplifier joined to the match line; and a selection circuit that can select the output of the match amplifier in accordance with the value of the word line.

Abstract: A data processing system includes a likelihood input operable to receive encoded data, a decoder operable to apply a decoding algorithm to likelihood values for the received encoded data and to yield a decoded output, and a decoder input initialization circuit operable to generate new decoder input values based in part on the likelihood values for the received encoded data after the likelihood values for the received encoded data have failed to converge in the decoder.

Abstract: Embodiments disclosed herein provide systems, methods, and computer readable media for storing data to a plurality of physical storage volumes. In a particular embodiment, a method provides identifying first data for storage on the plurality of physical storage volumes. Each of the plurality of storage volumes corresponds to respective ones of a plurality of data channels. The method further provides segmenting the first data into a plurality of data segments corresponding to respective ones of the plurality of data channels and transferring the plurality of data segments as respective bit streams over the respective ones of the plurality of data channels to the respective ones of the plurality of physical storage volumes. The plurality of storage volumes stores the respective bit streams in the exact condition in which the bit streams are received.

Abstract: Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone.