Abstract: Data to be stored at a memory sub-system can be received from a host system. A portion of the host data that includes user data and another portion of the host data that includes system metadata can be determined. A mapping for a data structure can be received that identifies locations of the data structure that are fixed with respect to an encoding operation and locations of the data structure that are not fixed with respect to the encoding operation. The data structure can be generated for the user data and system metadata based on the mapping, and an encoding operation can be performed on the data structure to generate a codeword.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry. The computing device issues a set of write requests to a first storage unit (SU) set based on a set of encoded data slices (EDSs) associated with a data object to be stored therein. When a write threshold number and fewer than all of the set of EDSs have been successfully stored, the computing device determines to store temporarily within a second SU set remaining EDS(s) that has not been successfully stored within the first SUs set and facilitates temporary storage thereof within the second SU set. Upon recovery of the EDS(s) from the temporary storage within the second SU set, the computing device issues additional write request(s) to the first SU set based on the EDS(s).

Abstract: A method for controlling a resistive random access memory (ReRAM) is proposed. The method calculates a number of a bit value of a data when the data is to be written to the resistive random access memory. Each bit of the data is flipped and the data is written to the ReRAM if the number of the bit value is greater than a half of a length of the data. The data as it original is written to the ReRAM if the number of the bit value is less than a half of the length of the data.

Abstract: User data that is to be stored at a memory system can be received. System data associated with the memory system can be identified and the user data and the system data can be stored at the memory system based on an error control operation. A subset of the system data can be identified and the subset of the system data can be stored at the memory system based on another error control operation.

Abstract: An encoding method includes: processing a plurality of data blocks to generate a plurality of partial parity blocks, wherein the partial parity blocks includes a first portion and a second portion; using a first computing circuit to generate a first calculating result according to the second portion of the partial parity blocks; using the first calculating result to adjust the first portion of the partial parity blocks; performing circulant convolution operations upon the adjusted first portion to generate a first portion of parity blocks; and using a second computing circuit to generate a second portion of the parity blocks according to at least the first portion of parity blocks; wherein the first portion of the parity blocks and the second portion of the parity blocks serve as a plurality of parity blocks generated in response to encoding the data blocks.

Abstract: Embodiments of this application provide a method for processing information bits. A communication device obtains K information bits and a code length M. The code length M is a length of an output sequence resulting from processing the information bits. The communication device generates an N-bit bit sequence that includes the K information bits and one or more parity check bits, encodes the bit sequence using a polar encoding formula to obtain an N-bit encoded sequence, rate matches the encoded sequence to obtain the output sequence, modulates the rate matched sequence to obtain output sequence and outputs the output sequence. When M?K>192, in the bit sequence, one of the parity check bits is placed in a bit position that is determined according to reliabilities of the bit positions in the bit sequence for placing the K information bits and the one or more parity check bits.

Abstract: A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A-10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance.

Abstract: A receiver device generates a bit stream corresponding to a received signal at least by demodulating the received signal. The received signal includes an address that was encoded at a transmitter device using a forward error correction code. The receiver device correlates the bit stream with an encoded known address to generate a correlation output that indicates a degree of similarity between a segment of the bit stream and the encoded known address. The encoded known address corresponds to a known device address that was encoded using the error correction code. The receiver device determines when the correlation output is greater than a threshold that corresponds to a particular degree of similarity with the encoded known address. The receiver device determines that the bit stream includes the known device address when the receiver device determines that the correlation output is greater than the threshold.

Abstract: A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A?10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance.

Abstract: A decompression apparatus is provided. The decompression apparatus includes a memory configured to store compressed data decompressed and used in neural network processing of an artificial intelligence model, a decoder configured to include a plurality of logic circuits related to a compression method of the compressed data, decompress the compressed data through the plurality of logic circuits based on an input of the compressed data, and output the decompressed data, and a processor configured to obtain data of a neural network processible form from the data output from the decoder.

Abstract: A data storage system includes a processing circuit, a calculating circuit and an encoding circuit. The processing circuit receives a data byte from a host. The calculating circuit generates a cyclic redundancy check code according to an LBA, and combines the cyclic redundancy check code and the data byte into a data sector so that the data sector includes LBA-related information. The encoding circuit encodes the data sector to generate an error checking and correcting code, and combines the data sector and the error checking and correcting code into a storage data, so that the storage data includes the LBA-related information without including the LBA. Via the data sector and the storage data, the data storage system performs cyclic redundancy checking as well as error checking and correcting without storing the LBA for reducing 1-bit errors; and the LBA-related information does not include part or all of the LBA.

Abstract: A first device may establish, with a second device, a logical link associated with short-range communications. The first device may receive a first packet carried on the logical link. When the first PDU data fails the decoding check, the first device may determine, based on the logical link, a first operational mode from a plurality of operational modes for error correction, the first device may receive a set of retransmission packets on the logical link, each of the set of retransmission packets including respective PDU data that is a retransmission of the first PDU data, and the first device may apply, based on the first PDU data included in the first packet and the respective PDU data included in each of the set of retransmission packets, the first operational mode for error correction.

Abstract: A distributed storage system can use a high rate MSR erasure code to repair multiple nodes when multiple node failures occur. An encoder constructs m r-ary trees to determine the symbol arrays for the parity nodes. These symbol arrays are used to generate the parity data according to parity definitions or parity equations. The m r-ary trees are also used to identify a set of recovery rows across helper nodes for repairing a systematic node. When failed systematic nodes correspond to different ones of the m r-ary trees, a decoder may select additional recovery rows. The decoder selects additional recovery rows when the parity definitions do not provide a sufficient number of independent linear equations to solve the unknown symbols of the failed nodes. The decoder can select recovery rows contiguous to the already identified recovery rows for access efficiency.

Abstract: A method for execution by a storage unit includes identifying, from a plurality of memory devices of the storage unit, a first memory device that is designated for storage of a first data slice to be written of the storage unit based on determining a slice name of the first data slice compares favorably to a namespace assigned to the first memory device. A function is performed on the slice name of the first data slice to identify a second memory device from the plurality of memory devices of the storage unit for temporary storage the first data slice in response to determining that the first memory device is unavailable and the first data slice is stored in the second memory device in response. The first data slice is migrated to storage in the first memory device in response to determining that the first memory device is available.

Abstract: A method for execution by a storage unit includes identifying, from a plurality of memory devices of the storage unit, a first memory device that is designated for storage of a first data slice to be written of the storage unit based on determining a slice name of the first data slice compares favorably to a namespace assigned to the first memory device. A function is performed on the slice name of the first data slice to identify a second memory device from the plurality of memory devices of the storage unit for temporary storage the first data slice in response to determining that the first memory device is unavailable and the first data slice is stored in the second memory device in response. The first data slice is migrated to storage in the first memory device in response to determining that the first memory device is available.

Abstract: Methods, systems, and devices for wireless communications are described. An encoder of a wireless device may receive a number of information bits and a block size for transmission. If the block size is not a power of two, the encoder may round the block size up to the nearest power of 2, generate a larger codeword, and puncture the excess bits. The punctured bits may affect a rate of polarization when generating a polar code, and sub-blocks with a high number of punctured bits may produce too few sufficiently polarized channels. The encoder may implement a capacity backoff when polar coding to identify a greater number of polarized channels. The encoder may assign information bits to sufficiently polarized channels of the greater number of polarized channels.

Abstract: The invention relates to the field of wireless communication technology, and in particular, to a method and device for transmitting and receiving feedback information, resolving a problem of providing ACK/NACK feedback of a physical uplink shared channel (PUSCH) transmission in an uplink pilot time slot (UpPTS). In one embodiment of the invention, the method comprises: a terminal transmits, in a special subframe n, PUSCH data, and receive, in a subframe (n+kPHICH), physical hybrid-ARQ indicator channel (PHICH) data corresponding to the PUSCH data, wherein a PHICH is used to carry feedback information of the PUSCH data; and a network apparatus receives, in the special subframe n, the PUSCH data, and transmits, in the subframe (n+kPHICH), the PHICH data corresponding to the PUSCH data. Therefore, the embodiment implements transmission of ACK/NACK of PUSCH data in an UpPTS.

Abstract: A method for decoding an error correction code and an associated decoding circuit are provided, where the method includes the steps of: calculating a set of error syndromes of the error correction code, where the error correction code is a t-error correcting code and has capability of correcting t errors, and a number s of the set of error syndromes is smaller than t; sequentially determining a set of coefficients within a plurality of coefficients of an error locator polynomial of the error correction code according to at least one portion of error syndromes within the set of error syndromes for building a roughly-estimated error locator polynomial; performing a Chien search to determine a plurality of roots of the roughly-estimated error locator polynomial; and performing at least one check operation to selectively utilize a correction result of the error correction code as a decoding result of the error correction code.

Abstract: An infrastructure equipment that transmits signals representing data via a wireless access interface to a communications device and receives signals representing data via the wireless access interface from the communications device in accordance with a time divided structure in which the wireless access interface is divided into a plurality of repeating time units. The infrastructure equipment provides, in each of a first plurality of the time units, one of a plurality of control channels each configured to schedule one of a plurality of data channels, and provides, in each of a second plurality of time units of the signal transmitted to the communications device, one of the plurality of data channels, the plurality of data channels being formed of one or more bundles of data channels, wherein the infrastructure equipment transmits a bundle status indicator in one or more of the plurality of control channels.

Abstract: Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like.