Abstract: An electronic device may include first through fourth current generators. The first current generator may be configured to output first and second mirroring currents. The second current generator may be configured to output third and fourth mirroring currents. The third current generator may be configured to generate a fifth mirroring current having a current slope proportional to a current slope of the first mirroring current and output a first current having a level of a value obtained by subtracting a level of the fifth mirroring current from a level of the second mirroring current. The fourth current generator may be configured to generate a sixth mirroring current having a current slope proportional to a current slope of the fourth mirroring current and output a second current having a level of a value obtained by subtracting a level of the sixth mirroring current from a level of the third mirroring current.

Abstract: A step up/down inverter circuit (10) is provided with: a plus line (13p) and a minus line (13m) connected to the plus terminal and minus terminal of a DC power supply, respectively; a voltage dividing circuit (14), a first leg (15), and a second leg (16) which are disposed between the plus line (13p) and the minus line (13m); a first reactor L1, having one end connected to a first intra-leg wiring connecting the switching elements SW1, 2 of the first leg (15); a second reactor L2, having one end connected to second intra-leg wiring connecting the switching elements SW3, 4 of the second leg (16) and having the other end connected to the other end of the first reactor (L1); a bidirectional switching element SW5 disposed between the first intra-leg wiring and a w-terminal (12w); another bidirectional switching element SW6 disposed between the second intra-leg wiring and a u-terminal (12u); and a smoothing circuit (17) for smoothing the voltages output from the bidirectional switching elements SW5, 6.

Abstract: A solid state light source driver circuit that operates in either a buck convertor or a boost convertor configuration is provided. The driver circuit includes a controller, a boost switch circuit and a buck switch circuit, each coupled to the controller, and a feedback circuit, coupled to the light source. The feedback circuit provides feedback to the controller, representing a DC output of the driver circuit. The controller controls the boost switch circuit and the buck switch circuit in response to the feedback signal, to regulate current to the light source. The controller places the driver circuit in its boost converter configuration when the DC output is less than a rectified AC voltage coupled to the driver circuit at an input node. The controller places the driver circuit in its buck converter configuration when the DC output is greater than the rectified AC voltage at the input node.

Abstract: Systems and methods for operating a power converter with a plurality of inverter blocks with silicon carbide MOSFETs are provided. A DC to AC converter can include a plurality of inverter blocks. Each inverter block can include a plurality of switching devices. A control method can include identifying one of a plurality of switching patterns for operation of the inverter block for each inverter block. Each switching pattern can include a plurality of switching commands. The control method can further include controlling each inverter block based on the identified switching pattern for the inverter block. The control method can further include rotating the switching patterns among the plurality of inverter blocks.

Abstract: A switched resonant power converter includes multiple switching transistors, a resonant circuit comprising a capacitor and an inductor, and an auxiliary soft-start bypass circuit that bypasses a default switching path that includes a first switching transistor of the switching transistors, and provides an alternative path through an impedance element. A corresponding control circuit is configured to switch between an operational mode in which the default switching path is periodically activated while the alternative path is deactivated to provide a first frequency-responsive power through the resonant circuit, and a soft-start mode in which the alternative path is periodically activated while the default switching path is deactivated to provide a second frequency-responsive power through the resonant circuit.

Abstract: Provided is a voltage regulator capable of stably suppressing overshoot. The voltage regulator includes a non-regulated state detection circuit for detecting a non-regulated state, and an overshoot suppression circuit. The overshoot suppression circuit is configured to operate when the non-regulated state detection circuit detects the non-regulated state.

Abstract: An exemplary embodiment of an alternating valley switching controller is provided. The alternating valley switching controller includes a valley detection circuit and an alternating circuit. The valley detection circuit is coupled to an auxiliary winding of a transformer to generate a valley-detection signal. The alternating circuit alternates a plurality of switching periods of a switching signal according to a blanking-window signal and the valley-detection signal. The blanking-window signal switches between a first voltage level and a second voltage level in the plurality of switching periods. The plurality of switching periods includes at least two first periods and at least two second periods which occur alternately in response to the first voltage level and the second voltage of the blanking-window signal.

Abstract: A DC/DC converter is provided for operation within a narrow voltage range during normal conditions, while allowing for a wider input voltage range for short periods of time. A first switch is coupled across first and second input terminals, and a capacitor is coupled in parallel with the first switch and across the input terminals. A second switch is coupled in series with the first input terminal and between the first switch and the capacitor. Operation of the switches is regulated in accordance with a bypass mode of operation when received input power is within a defined range, and a boost mode of operation when received input power is less than a threshold value, wherein the received input power is boosted to a bulk output power within the defined range. Boost operations may in various embodiments be provided via, for example, a critical conduction scheme or continuous conduction scheme.

Abstract: This application relates to a circuit for generating an output voltage and regulating the output voltage to a target voltage. The circuit includes a switchable voltage divider circuit configured to generate a feedback voltage that is a variable fraction of the output voltage, an error amplifier stage configured to generate a control voltage on the basis of a reference voltage and the variable fraction of the output voltage, a buffer stage configured to generate the output voltage on the basis of the control voltage, and a charge injection circuit configured to inject charge at an intermediate node between the error amplifier stage and the buffer stage to thereby modify the control voltage generated by the error amplifier stage. The application further relates to a method of operating such circuit.

Abstract: A DC-to-DC converter and a PWM device thereof are provided. The PWM device includes a ramp generator circuit, an error amplifier, a comparator and a clamping circuit. The error amplifier compares a voltage difference between the feedback voltage and the reference voltage to output a comparison voltage corresponding to the voltage difference. The comparator compares a ramp voltage of the ramp generator circuit and the comparison voltage of the error amplifier, so as to output a pulse signal. The clamping circuit determines whether to induce the comparison voltage to follow the ramp voltage. The clamping circuit is disabled when the PWM device is operated in the PWM mode, such that the comparison voltage and the ramp voltage are independent of each other. The clamping circuit is enabled when the PWM device is operated in the non-PWM mode, such that the comparison voltage follows the ramp voltage.

Abstract: Power supply units (PSU) provide for digital current-sharing loop control to ensure output voltage regulation during dynamic load transients by (i) delaying an internal current signal to match a delay in a shared current signal, and (ii) controlling the output amplifier based on the shared current signal and the delayed local current signal to maintain the respective local DC electrical power in proportion to contributions by other ones of the more than one PSU to the shared DC electrical power and thereby avoid instability in dynamic response to a load transient induced by the power consuming component.

Abstract: A method and circuit are provided for implementing voltage sense point switching for regulators. A regulator voltage sensing circuit includes at least two sense points enabling a regulator to compensate for voltage drop at the sense points and providing at least one of the sense points at a location to be switched. Switched loads have gains at the sense points to compensate for the voltage drop in a transistor switch at maximum load. A non-switched output is sensed and functions as an over-voltage protection to limit the transistor switch voltage drop.

Abstract: A multiphase power converter has a plurality of phase circuits, each of which provides a phase current when being active. During single-phase operation of the multiphase power converter, an enhanced phase control circuit and method monitor the summation of the phase currents, and when the summation becomes higher than a threshold, switch the multiphase power converter to a higher power zone to increase the number of active phases. A high efficiency and high reliability multiphase power converter is thus accomplished.

Abstract: A planar matrix transformer assembly. In one embodiment, the assembly comprises (a) a core comprising multiple center posts in a matrix pattern; and multiple edge posts along edges of the core for a magnetic flux return path; (b) a single-turn layer comprising a top winding on the top the layer to form a single turn around each center post; and a bottom winding electrically coupled to the top winding and on the bottom of the layer to form a single turn around each center post; and (c) a multi-turn layer comprising multiple top-side windings on top of the layer, wherein each top-side winding is a multi-turn winding around a different center post; and multiple bottom-side windings on the bottom of the multi-turn layer, wherein each bottom-side winding is (i) electrically coupled to a different top-side winding in a one-to-one correspondence, and (ii) a multi-turn winding around a different center post.

Abstract: Generally, this disclosure provides circuitry and methods for determining the output capacitance of an output load capacitor of a power supply. The output capacitance is generally determined by beginning a calibration period and charging an output capacitor with a current source to generate an output voltage. The output voltage may be compared to a reference voltage, and a time period is determined during which the output voltage is less than the reference voltage. The capacitance value, C, of the output capacitor may be determined based on, at least in part, the determined time period. This disclosure also provides circuitry and methods to adjust certain parameters of the power supply based on the determined C value. For example, in a ramp compensation portion of the power supply, the value of a ramp capacitor and/or reset resistor may be adjusted once the value of C is determined.

Abstract: A first capacitor and an auxiliary power supply are provided to a secondary side of an insulated synchronous rectification DC/DC converter, in addition to a synchronous rectification transistor and a secondary-side controller. One end of the first capacitor is connected to a first node that connects the synchronous rectification transistor and a secondary winding. The auxiliary power supply charges the first capacitor using the voltage VOUT supplied via the output line, so as to stabilize the voltage across the first capacitor. The ground voltage is supplied to the secondary-side controller via the first node. Furthermore, the power supply voltage is supplied to the secondary-side controller via the other end of the first capacitor.

Abstract: The present application relates to power converters, particularly switch mode power converters sharing a load in which the converters are operated to share stresses between them. The application provides a controller (108) in which a stress share control loop (108a, 108b) is provided to ensure the associated converter is operating at an average stress. The stress share control loop has a proportional and an integral term in its feedback path. The integral term may be enabled or disabled. In use, the integral term is enabled in all but one controller.

Abstract: A power converter provides a low-voltage output using a full-bridge fault-tolerant rectification circuit. The output circuit uses controlled switches as rectifiers. A fault detection circuit monitors circuit conditions. Upon detection of a fault, the switches are disabled decoupling the power converter from the system. A common-source dual MOSFET device includes a plurality of elements arranged in alternating patterns on a semiconductor die. A common-source dual synchronous rectifier includes control circuitry powered from the drain to source voltage of the complementary switch. A DC-to-DC transformer converts power from an input source to a load using a fixed voltage transformation ratio. A clamp phase may be used to reduce power losses in the converter at light loads, control the effective output resistance of the converter, effectively regulate the voltage transformation ratio, provide narrow band output regulation, and control the rate of change of output voltage for example during start up.

Abstract: To provide a soft start circuit capable of obtaining a high-accuracy soft start time. The soft start circuit is equipped with a constant current source, an output terminal which outputs a soft start voltage, a ground terminal, a first transistor which is connected between the constant current source and the ground terminal and has a gate and a drain both short-circuited, a second transistor which is connected between the constant current source and the output terminal and receives a clock signal at a gate thereof, and a capacitor connected between the second transistor and the ground terminal.

Abstract: A semiconductor device for limiting inrush current in hot-swap applications includes a power transistor and a current sensing circuit. The power transistor has a first terminal, a second terminal and a control terminal, wherein the first terminal is configured to receive an input voltage from a power supply, the second terminal is configured to provide an output voltage to a load, the control terminal is configured to receive a control voltage. Under regulation of the control voltage, the output voltage increases gradually towards the input voltage during a startup period and becomes substantially equal to the input voltage in a steady state. The current sensing circuit senses the current flowing through the power transistor and generates a current sensing signal. In order to achieve current balance, the control voltage is adjusted based on the relationship between the current sensing signal and current sensing signals of other semiconductor devices connected in parallel with the semiconductor device.