Abstract: An example fused convolutional layer, comprising, a comparator capable of reception of a first zero point and a multiply-accumulation result, a first multiplexer coupled to the comparator, wherein the first multiplexer receives a plurality of power-of-two exponent values, a shift normalizer, coupled to the first multiplexer, wherein the shift normalizer is capable of receiving the multiply-accumulation result and the plurality of power-of-two exponent values, wherein the shift normalizer limits a quantization of the multiply-accumulation result to a power-of-two scale and a second multiplexer coupled to an output of the shift normalizer, the first multiplexer and receives a second zero point and outputs an activation.

Abstract: A pseudo speckle pattern generation apparatus includes a light source, a beam expander, and a spatial light modulator. The spatial light modulator has an intensity modulation distribution based on a pseudo speckle pattern calculated from a pseudo random number pattern and a correlation function, receives light output from the light source and increased in beam diameter by the beam expander, spatially modulates the received light according to the modulation distribution, and outputs modulated light.

Abstract: An artificial neural network (ANN) accelerator is provided. The ANN accelerator includes digital controlled oscillators (DCOs), digital-to-time converters (DTCs) and a mixed-signal multiply-and-accumulate (MAC) array. Each DCO generates a first analog operand signal based on a first digital data value, and transmits the first analog operand signal along a respective column signal line. Each DTC generates a second analog operand signal based on a second digital data value, and transmits the second analog operand signal along a respective row signal line. The mixed-signal MAC array is coupled to the row and column signal lines, and includes mixed-signal MAC units. Each mixed-signal MAC unit includes an integrated clock gate (ICG) that generates a digital product signal based on the first and second analog operand signals, and a counter circuit that increments or decrements a count value stored in a register based on the digital product signal.

Abstract: A floating point multiplier-accumulator (MAC) multiplies and accumulates N pairs of floating point values using N MAC processors operating simultaneously, each pair of values comprising an input value and a coefficient value to be multiplied and accumulated. The pairs of floating point values are simultaneously processed by the plurality of MAC processors, each of which output a signed integer form fraction with a first bitwidth and a second bitwidth, along with a maximum exponent. The first bitwidth signed integer form fractions are summed by an adder tree using the first bitwidth to form a first sum, and when an excess leading 0 condition is detected, a second adder tree operative on the second bitwidth integer form fractions forms a second sum. The first sum or second sum, along with the maximum exponent, is converted into floating point result.

Abstract: In a general aspect, an optimization problem is solved using a hybrid computing system. A classical processor unit receives a first data structure that represents the optimization problem. The classical processor unit executes a branch-and-bound process on the first data structure to generate values for a first subset of elements of a solution to the optimization problem. A second data structure is generated based on the first data structure and the first subset of elements. The second data structure represents a reduced version of the optimization problem. A quantum processor unit and a classical processor unit are used to execute a quantum approximate optimization algorithm (QAOA) on the second data structure to generate values for a second subset of the elements of the solution to the optimization problem. The first subset and second subset are combined to obtain the solution to the optimization problem.

Abstract: The invention relates to a method for filtering a numerical input signal sampled at a sampling frequency in order to obtain a filtered signal, the method being performed by a radar system and including at least one step for obtaining a first (respectively second) output signal by carrying out first (respectively second) operations on the first (respectively second) processing channel, the first (respectively second) operations including at least the application of a discrete Fourier transform to M/2 points on a signal coming from the input signal, and applying an inverse discrete Fourier transform to M/2 points on the first signal in order to obtain M points of the spectrum of the first signal, M being an integer strictly greater than 2, the application step being carried out by the addition of the results of two processing channels.

Abstract: Aspects of the invention include physical design-optimal Dadda architectures that scale with increasing operand size. Partial product arrays can be generated for two n-bit operands and columns in the partial product arrays can be shifted to a first row. The number of partial products in each column can be iteratively reduced across one or more stages until each column has at most two partial products. At each stage a maximum column height is determined and each column having a height greater than the maximum column height is reduced using half-adders and full-adders. Result bits of the half-adders and the full-adders are placed at the bottom of the current column and carry bits of the half-adders and the full-adders are placed at the bottom of the next column.

Abstract: Linear-feedback shift registers (LFSRs) for generating bounded random numbers (e.g., random numbers within a narrower range than those generated by a conventional LFSR of the same width) are described. In one embodiment, a bounded LFSR for generating an n-bit value comprises an m-bit LFSR with a range of 2m random numbers and an n?m bit LFSR with a range of 2n-m?1?k random numbers. The bounded LFSR further comprises logic to skip k values from a repeatable sequence of the n?m bit LFSR, which can, for example, be configured during the design of the bounded LFSR. The bounded LFSR provides bounded random numbers based on the outputs of the m-bit LFSR and the n?m bit LFSR. In one embodiment, the bounded random number generated by the bounded LFSR is used as a random address in a row hammer mitigation system.

Abstract: Certain aspects of the present disclosure provide a method, including: storing a depthwise convolution kernel in a first one or more columns of a CIM array; storing a fused convolution kernel in a second one or more columns of the CIM array; storing pre-activations in one or more input data buffers associated with a plurality of rows of the CIM array; processing the pre-activations with the depthwise convolution kernel in order to generate depthwise output; modifying one or more of the pre-activations based on the depthwise output to generate modified pre-activations; and processing the modified pre-activations with the fused convolution kernel to generate fused output.

Abstract: A system performs matrix multiplication of a vector by a two-dimensional matrix by evaluating whether the vector includes zero values. Rows of the matrix are loaded into a first memory device from a second device. Rows corresponding to the indexes of the zero values are not loaded. A dot product of columns of the matrix and the input vector is performed and stored. The matrix may be stored in the second memory device such that only entries for non-zero entries are stored. The rows of the matrix may be reconstructed in the first memory device from these entries.

Abstract: There are provided methods and apparatus for performing modified cosine transformation (MDCT) with an analysis/synthesis windowing function, using an analysis windowing function having a meandering portion which passes a linear function in correspondence of at least four points.

Abstract: An architecture for a chopper stabilized multiplier-accumulator (MAC) uses a chop clock and common Unit Element (UE), the MAC formed as a plurality of MAC UEs receiving X and W values and a sign bit exclusive ORed with the chop clock, a plurality of Bias UEs receiving E value and a sign bit exclusive ORed with the chop clock, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

Abstract: This application describes hybrid hardware accelerators, systems, and apparatus for performing various computations in neural network applications using the same set of hardware resources. An example accelerator may include weight selectors, activation input interfaces, and a plurality of Multiplier-Accumulation (MAC) circuits organized as a plurality of MAC lanes Each of the plurality of MAC lanes may be configured to: receive a control signal indicating whether to perform convolution or vector operations; receive one or more weights according to the control signal; receive one or more activations according to the control signal; and generate output data based on the one or more weights and the one or more input activations according to the control signal and feed the output data into an output buffer. Each of the plurality of MAC lanes includes a plurality of multiplier circuits and a plurality of adder-subtractor circuits.

Abstract: A signal processing apparatus includes a storage processing part that performs storage processing on data represented in a second representation format, wherein, when a value of the data is positive or zero, the second representation format is identical to a representation format of two's complement, while, when the value of the data is negative, the second representation format is a representation format in which all bits other than a most significant bit indicating a sign in a two's complement representation of the data are inverted, and an operation processing part that performs operation processing on at least any one of data represented in the two's complement representation or data obtained by applying compensation processing to data represented in the second representation format.

Abstract: Configurable circuits include an input selection region, a computation region, a switching region, and an output region. The input selection region includes a set of input multiplexers and selects and routes input signals. The computation region includes a set of lookup tables, each lookup table being coupled to selected signals from the input selection stage to generate a respective output signal. The switching region includes a set of output multiplexers, each output multiplexer being coupled to output signals from the set of lookup tables to provide circuit outputs responsive to respective output selection signals. The output region includes a domino logic stage, having a set of transistors, coupled to output signals from the set of lookup tables to provide circuit outputs that determine combinations of the signals output by the set of lookup tables.

Abstract: The present description concerns a method of generation of a sequence of pseudo-random digital codes enabling to perform a permutation (3) of a first set of values (V) into a second set of values (Vp) based on said digital codes (CPos) representative of positions (j) of values (Vi) of the first set in the second set, including the steps of: generating, by successive iterations, a chain of numbers, called seed numbers, from an initial pseudo-random seed number (W0) by application of a first function (24,26) from a seed number to the next seed number; applying a second function to each seed number of the chain to obtain each position code (CPos(j)), the second function including at least one permutation (PERM) followed by a bijection (BIJ).

Abstract: A vector dot product multiplier receives a row vector and a column vector as floating point numbers in a format of sign plus exponent bits plus mantissa bits. The dot product multiplier generates a single dot product value by separately processing the sign bits, exponent bits, and mantissa bits in a few pipelined stages. A first pipeline stage generates a sign bit, a normalized mantissa formed by multiplying pairs multiplicand elements, and exponent information. A second pipeline stage receives the multiplied pairs of normalized mantissas, performs an adjustment, performs a padding, complement, and shift, and sums the results in an adder stage. The resulting integer is normalized to generate a sign bit, exponent, and mantissa of the floating point result.

Abstract: An information processing apparatus includes an annealing control unit, a spin interaction memory, a random number generation unit, and a spin state update unit and obtains a solution by using an Ising model. The annealing control unit controls an annealing step and a parameter of a temperature and a parameter of a self-action. The spin interaction memory stores the interaction coefficient of a spin. The random number generation unit generates a predetermined random number. The spin state update unit includes a spin buffer that stores values of a plurality of spins, an instantaneous magnetic field calculation unit that calculates instantaneous magnetic fields of the plurality of spins, a probability calculation unit that calculates update probabilities of the plurality of spins, and a spin state determination unit that updates the values of the spins based on the update probabilities and a random number.

Abstract: Folded integer multiplier (FIM) circuitry includes a multiplier configurable to perform multiplication and a first addition/subtraction unit and a second addition/subtraction unit both configurable to perform addition and subtraction. The FIM circuitry is configurable to determine each product of a plurality of products for a plurality of pairs of input values having a first number of bits by performing, using the first and second addition/subtraction units, a plurality of operations involving addition or subtraction, and performing, using the multiplier, a plurality of multiplication operations involving values having fewer bits than the first number of bits. The plurality of multiplication operations includes a first number of multiplication operations, and the multiplier is configurable to begin performing all multiplication operations of the plurality of multiplication operations within a first number of clock cycles equal to the first number of multiplication operations.

Abstract: Disclosed is an apparatus and method for performing deep learning operations. The apparatus includes a systolic array comprising multiplier accumulator (MAC) units, and a control circuit configured to control an operation of a multiplexer connected to at least one of the MAC units and operations of the MAC units according to a plurality of operation modes.