Patents Examined by Jyoti Mehta
  • Patent number: 10394678
    Abstract: A processor core includes a decode circuit to decode an instruction. The processor core further includes a monitor circuit, where the monitor circuit includes a data structure to store a plurality of entries for addresses that are being monitored by the monitor circuit and a triggered queue to store a plurality of addresses for which a triggering event occurred. The processor core further includes an execution circuit to execute the decoded instruction to dequeue an address from the triggered queue and return the dequeued address in response to a determination that the triggered queue is not empty.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 27, 2019
    Assignee: INTEL CORPORATION
    Inventors: Wim Heirman, Yves Vandriessche
  • Patent number: 10372447
    Abstract: An instruction defined to be a looping instruction is obtained and processed. A determination is made as to whether an obtained selected character is an expected selected character. Based on the obtained selected character being the expected selected character, an execution process is used that includes a sequence of operations to perform an operation, the sequence of operations replacing a loop and providing a non-looping sequence to perform the operation on up to a defined number of units of data. The sequence of operations is configured to repeat one or more times and to terminate based on the obtained selected character. Based on the obtained selected character being different than the expected selected character, an alternate execution process is chosen.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 10372448
    Abstract: An instruction defined to be a looping instruction is obtained and processed. A determination is made as to whether an obtained selected character is an expected selected character. Based on the obtained selected character being the expected selected character, an execution process is used that includes a sequence of operations to perform an operation, the sequence of operations replacing a loop and providing a non-looping sequence to perform the operation on up to a defined number of units of data. The sequence of operations is configured to repeat one or more times and to terminate based on the obtained selected character. Based on the obtained selected character being different than the expected selected character, an alternate execution process is chosen.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 10365928
    Abstract: Embodiments of the invention are directed to methods for handling scratch registers in a processor. The method includes receiving a cracked instruction in an instruction dispatch unit of the processor. The method further includes decoding the cracked instruction into a group of micro-operations. Based on a determination that the instruction group uses a scratch register, determining if the scratch register is used in other groups of micro-operations. Based on a determination that the scratch register is not used in other instruction groups, allocating a physical register for use as the scratch register without creating a mapper entry for the scratch register.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory W. Alexander, David S. Hutton, Christian Jacobi, Edward T. Malley, Anthony Saporito
  • Patent number: 10360162
    Abstract: Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: July 23, 2019
    Assignee: NXP USA, Inc.
    Inventors: Daniel M. McCarthy, Joseph C. Circello, Kristen A. Hausman
  • Patent number: 10353708
    Abstract: Systems, apparatuses, and methods for utilizing efficient vectorization techniques for operands in non-sequential memory locations are disclosed. A system includes a vector processing unit (VPU) and one or more memory devices. In response to determining that a plurality of vector operands are stored in non-sequential memory locations, the VPU performs a plurality of vector load operations to load the plurality of vector operands into a plurality of vector registers. Next, the VPU performs a shuffle operation to consolidate the plurality of vector operands from the plurality of vector registers into a single vector register. Then, the VPU performs a vector operation on the vector operands stored in the single vector register. The VPU can also perform a vector store operation by permuting and storing a plurality of vector operands in appropriate locations within multiple vector registers and then storing the vector registers to locations in memory using a mask.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 16, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anupama Rajesh Rasale, Dibyendu Das, Ashutosh Nema, Md Asghar Ahmad Shahid, Prathiba Kumar
  • Patent number: 10338921
    Abstract: An asynchronous instruction execution apparatus and method are provided. The asynchronous instruction execution apparatus includes a vector execution unit control VXUC module and n vector execution unit data VXUD modules, where n is a positive integer. The VXUC module is configured to perform instruction decoding and token management. The n VXUD modules are cascaded, separately connected to the VXUC module, and configured to invoke an external calculation resource to perform data calculation. A bit width of data processed by the asynchronous instruction execution apparatus is M, a bit width of each VXUD module is N, and n=M/N. The asynchronous instruction execution apparatus is divided into two parts: the VXUC and the VXUD.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: July 2, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Shaola Yang, Xiaocheng Liu, Zhen Xu
  • Patent number: 10324717
    Abstract: An instruction defined to be a looping instruction is obtained and processed. A determination is made as to whether an obtained selected character is an expected selected character. Based on the obtained selected character being the expected selected character, an execution process is used that includes a sequence of operations to perform an operation, the sequence of operations replacing a loop and providing a non-looping sequence to perform the operation on up to a defined number of units of data. The sequence of operations is configured to repeat one or more times and to terminate based on the obtained selected character. Based on the obtained selected character being different than the expected selected character, an alternate execution process is chosen.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 10324716
    Abstract: An instruction defined to be a looping instruction is obtained and processed. A determination is made as to whether an obtained selected character is an expected selected character. Based on the obtained selected character being the expected selected character, an execution process is used that includes a sequence of operations to perform an operation, the sequence of operations replacing a loop and providing a non-looping sequence to perform the operation on up to a defined number of units of data. The sequence of operations is configured to repeat one or more times and to terminate based on the obtained selected character. Based on the obtained selected character being different than the expected selected character, an alternate execution process is chosen.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 10318296
    Abstract: A method and apparatus are provided for executing instructions of a multi-threaded processor having multiple hardware threads with differing hardware resources comprising the steps of receiving a plurality of streams of instructions and determining which hardware threads are able to receive instructions for execution, determining whether a thread determined to be available for executing an instructions has the hardware resources available required by that instructions and executing the instruction in dependence on the result of the determination.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: June 11, 2019
    Assignee: MIPS Tech, LLC
    Inventor: Andrew Webber
  • Patent number: 10311017
    Abstract: The present disclosure provides a reconfigurable processor and a timing control method thereof. The reconfigurable processor comprises a reconfigurable cell array (RCA) including a plurality of reconfigurable cells (RCs) and a control unit; the control unit is configured to generate and send a timing control information to the RCA; and the RCA is configured to execute an operation task according to the timing control information, wherein the RC in the RCA starts to execute an operation when receiving the timing control information, and delivers the timing control information to a next level of RC within the RCA according to a preset order after the operation is completed; and when the RCA completes the operation task corresponding to the timing control information, the RCA destroys the timing control information, wherein the operation task includes operations executed by each level of the RCs receiving the timing control information.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: June 4, 2019
    Assignee: Tsinghua University
    Inventors: Leibo Liu, Youyu Wu, Shaojun Wei
  • Patent number: 10282207
    Abstract: Operation of a multi-slice processor that includes execution slices and load/store slices coupled via a results bus includes: receiving, by an execution slice, a producer instruction, including: storing, in an entry of an issue queue, the producer instruction; and storing, in a register, an issue queue entry identifier representing the entry of the issue queue in which the producer instruction is stored; receiving, by the execution slice, a source instruction, the source instruction dependent upon the result of the producer instruction, including: storing, in another entry of the issue queue, the source instruction and the issue queue entry identifier of the producer instruction; determining in dependence upon the issue queue entry identifier of the producer instruction that the producer instruction has issued from the issue queue; and responsive to the determination that the producer instruction has issued from the issue queue, issuing the source instruction from the issue queue.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: May 7, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, Sundeep Chadha, Michael J. Genden, Jerry Y. Lu, Dung Q. Nguyen, Nasrin Sultana, David R. Terry, David S. Walder
  • Patent number: 10268482
    Abstract: Operation of a multi-slice processor that includes execution slices and load/store slices coupled via a results bus includes: receiving, by an execution slice, a producer instruction, including: storing, in an entry of an issue queue, the producer instruction; and storing, in a register, an issue queue entry identifier representing the entry of the issue queue in which the producer instruction is stored; receiving, by the execution slice, a source instruction, the source instruction dependent upon the result of the producer instruction, including: storing, in another entry of the issue queue, the source instruction and the issue queue entry identifier of the producer instruction; determining in dependence upon the issue queue entry identifier of the producer instruction that the producer instruction has issued from the issue queue; and responsive to the determination that the producer instruction has issued from the issue queue, issuing the source instruction from the issue queue.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, Sundeep Chadha, Michael J. Genden, Jerry Y. Lu, Dung Q. Nguyen, Nasrin Sultana, David R. Terry, David S. Walder
  • Patent number: 10241788
    Abstract: An apparatus including a queue configured to store a plurality of instructions and state information indicating whether each instruction of the plurality of instructions can be performed independently of older pending instructions; and a state-selection circuit configured to set a state information of each instruction of the plurality of instructions in view of an older pending instruction in the queue.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: March 26, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Tariq Kurd, John Redford
  • Patent number: 10235181
    Abstract: An out-of-order (OOO) processor includes ready logic that provides a signal indicating an instruction is ready when all operands for the instruction are ready, or when all operands are either ready or are marked back-to-back to a current instruction. By marking a second instruction that consumes an operand as ready when it is back-to-back with a first instruction that produces the operand, but the first instruction has not yet produced the operand, latency due to missed cycles in executing back-to-back instructions is minimized.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventor: Brian W. Thompto
  • Patent number: 10223126
    Abstract: An out-of-order (OOO) processor includes ready logic that provides a signal indicating an instruction is ready when all operands for the instruction are ready, or when all operands are either ready or are marked back-to-back to a current instruction. By marking a second instruction that consumes an operand as ready when it is back-to-back with a first instruction that produces the operand, but the first instruction has not yet produced the operand, latency due to missed cycles in executing back-to-back instructions is minimized.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventor: Brian W. Thompto
  • Patent number: 10209992
    Abstract: A method and system for branch prediction are provided herein. The method includes executing a program, wherein the program comprising multiple procedures, and setting bits in a taken branch history register to indicate whether a branch is taken or not taken during execution of instructions in the program. The method further includes the steps of calling a procedure in the program and overwriting, responsive to calling the procedure, the contents of the taken branch history register to a start address for the procedure.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: February 19, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Sophie Wilson, Geoffrey Barrett
  • Patent number: 10175980
    Abstract: A computing unit is disclosed, comprising a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs one or more computations associated with at least one element of a data array, the one or more computations being performed by the MAC operator and comprising, in part, a multiply operation of the input activation received from the data bus and a parameter received from the second memory bank.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: January 8, 2019
    Assignee: Google LLC
    Inventors: Olivier Temam, Ravi Narayanaswami, Harshit Khaitan, Dong Hyuk Woo
  • Patent number: 10169046
    Abstract: An instruction sequencing unit in an out-of-order (OOO) processor includes a Most Favored Instruction (MFI) mechanism that designates an instruction as an MFI. The processing queues in the processor identify when they contain the MFI, and assures processing the MFI. The MFI remains the MFI until it is completed or is flushed, and which time the MFI mechanism selects the next MFI.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Maarten J. Boersma, Robert A. Cordes, David A. Hrusecky, Jennifer L. Molnar, Brian W. Thompto, Albert J. Van Norstrand, Jr., Kenneth L. Ward
  • Patent number: 10169268
    Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventors: Mahesh Natu, Thanunathan Rangarajan, Gautam Doshi, Shamanna M. Datta, Baskaran Ganesan, Mohan J. Kumar, Rajesh S. Parthasarathy, Frank Binns, Rajesh Nagaraja Murthy, Robert C. Swanson