Patents Examined by Jyoti Mehta
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Patent number: 11392780Abstract: The analog multiplier includes a first signal input module, and a second signal input module or a third signal input module. The first signal input module is configured to output a frequency modulation signal. The second signal input module includes a first energy storage unit, a first switch unit, and a second switch unit. The first switch unit and the second switch unit are alternately turned on or turned off based on a frequency of the frequency modulation signal. The third signal input module includes a second energy storage unit, two third switch units, and two fourth switch units. The third switch unit and the fourth switch unit are alternately turned on or turned off based on the frequency of the frequency modulation signal.Type: GrantFiled: February 23, 2022Date of Patent: July 19, 2022Assignee: Halo Microelectronics Co., Ltd.Inventors: Xiaoliang Tan, Guanhua Li, Chuang Lan
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Patent number: 11366667Abstract: A microprocessor with a solution to instruction fetching failure is shown. The branch predictor and the instruction cache are decoupled by a fetch target queue. In response to instruction fetching failure of a target fetching address, the instruction cache regains the target fetching address from the fetch target queue to restart the failed instruction fetching.Type: GrantFiled: October 13, 2020Date of Patent: June 21, 2022Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.Inventor: Fangong Gong
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Patent number: 11360773Abstract: Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching is disclosed. An instruction processing circuit is configured to detect fetched performance degrading instructions (Pals) in a pre-execution stage in an instruction pipeline that may cause a precise interrupt that would cause flushing of the instruction pipeline. In response to detecting a PDI in an instruction pipeline, the instruction processing circuit is configured to capture the fetched PDI and/or its successor, younger fetched instructions that are processed in the instruction pipeline behind the PDI, in a pipeline refill circuit.Type: GrantFiled: June 22, 2020Date of Patent: June 14, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Rami Mohammad Al Sheikh, Michael Scott McIlvaine
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Patent number: 11347477Abstract: A memory circuit includes a number (X) of multiply-accumulate (MAC) circuits that are dynamically configurable. The MAC circuits can either compute an output based on computations of X elements of the input vector with the weight vector, or to compute the output based on computations of a single element of the input vector with the weight vector, with each element having a one bit or multibit length. A first memory can hold the input vector having a width of X elements and a second memory can store the weight vector. The MAC circuits include a MAC array on chip with the first memory.Type: GrantFiled: September 27, 2019Date of Patent: May 31, 2022Assignee: Intel CorporationInventors: Huseyin Ekin Sumbul, Gregory K. Chen, Phil Knag, Raghavan Kumar, Ram Krishnamurthy
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Patent number: 11340904Abstract: Disclosed herein are vector index registers in vector processors that each store multiple addresses for accessing multiple positions in vectors. It is known to use scalar index registers in vector processors to access multiple positions of vectors by changing the scalar index registers in vector operations. By using a vector indexing register for indexing positions of one or more operand vectors, the scalar index register can be replaced and at least the continual changing of the scalar index register can be avoided.Type: GrantFiled: May 20, 2019Date of Patent: May 24, 2022Assignee: Micron Technology, Inc.Inventor: Steven Jeffrey Wallach
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Patent number: 11334361Abstract: An apparatus has processing circuitry, and history storage circuitry to store local history records. Each local history record corresponds to a respective subset of instruction addresses and tracks a sequence of observed instruction behaviour observed for successive instances of instructions having addresses in that subset. Pointer storage circuitry to store a shared pointer shared between the local history records. The shared pointer indicates a common storage position reached in each local history record. Prediction circuitry determines predicted instruction behaviour for a given instruction address based on a selected portion of a selected local history record stored in the history storage circuitry. The prediction circuitry selects the selected local history record based on the given instruction address and selects the selected portion based on the shared pointer.Type: GrantFiled: March 2, 2020Date of Patent: May 17, 2022Assignee: Arm LimitedInventors: Yasuo Ishii, Joseph Michael Pusdesris, Muhammad Umar Farooq
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Patent number: 11314686Abstract: An integrated circuit is disclosed that includes a central processing unit (CPU), a random access memory (RAM) configured for storing data and CPU executable instructions, a first peripheral circuit for accessing memory that is external to the integrated circuit, a second peripheral circuit, and a communication bus coupled to the CPU, the RAM, the first peripheral circuit and the second peripheral circuit. The second peripheral circuit includes a first preload register configured to receive and store a first preload value, a first register configured to store first information that directly or indirectly identifies a first location where first instructions of a first task can be found in memory that is external to the integrated circuit, and a counter circuit that includes a counter value. The counter circuit can increment or decrement the counter value with time when the counter circuit is started. A first compare circuit is also included and can compare the counter value to the first preload value.Type: GrantFiled: May 15, 2019Date of Patent: April 26, 2022Assignee: NXP USA, Inc.Inventors: Michael Rohleder, George Adrian Ciusleanu, David Allen Brown, Jeffrey Freeman
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Patent number: 11256513Abstract: There is provided an apparatus that includes input circuitry to receive input data and output circuitry to output a sequence of instructions to be executed by data processing circuitry. Generation circuitry performs a generation process to generate the sequence of instructions using the input data. The sequence of instructions comprises an indirect control flow instruction having a field that indicates where a target of the indirect control flow instruction is stored. The generation process causes at least one of the instructions in the sequence of instructions to store a state of control flow speculation after execution of the indirect control flow instruction. The at least one of the instructions in the sequence of instructions that stores the state of control flow speculation is inhibited from being subject to data value speculation by the data processing circuitry.Type: GrantFiled: March 14, 2019Date of Patent: February 22, 2022Assignee: Arm LimitedInventors: Richard William Earnshaw, Kristof Evariste Georges Beyls, James Greenhalgh
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Patent number: 11256511Abstract: A method of performing instruction scheduling during execution in a processor includes receiving, at an execution unit of the processor, an initial assignment of an assigned execution resource among two or more execution resources to execute an operation. An instruction includes two or more operations. Based on determining that the assigned execution resource is not available, the method also includes determining, at the execution unit, whether another execution resource among the two or more execution resources is available to execute the operation. Based on determining that the other execution resource is available, the method further includes executing the operation with the other execution resource.Type: GrantFiled: May 20, 2019Date of Patent: February 22, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cedric Lichtenau, Stefan Payer, Kerstin Claudia Schelm, Anthony Saporito, Gregory William Alexander
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Patent number: 11249754Abstract: An apparatus and method for performing a packed horizontal addition of words and doublewords. One embodiment of a processor includes a decoder to decode a packed horizontal add instruction which includes an opcode and one or more operands used to identify a plurality of packed words; a source register to store a plurality of packed words; execution circuitry to execute the decoded instruction, and a destination register to store a final result as a packed result word in a designated data element position. The execution circuitry includes operand selection circuitry to identify first and second packed words from the source register in accordance with the operands and opcode; adder circuitry to add the two packed words to generate a temporary sum; a temporary storage of at least 17 bits to store the temporary sum; and saturation circuitry to saturate the temporary sum if necessary to generate the final result.Type: GrantFiled: December 21, 2017Date of Patent: February 15, 2022Assignee: Intel CorporationInventors: Venkateswara Madduri, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Mark Charney
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Patent number: 11249763Abstract: An arithmetic processing unit includes an instruction decoder which decodes a fetch instruction to issue an execution instruction; a reservation station which temporarily stores the execution instruction; and an arithmetic unit which executes the execution instruction, and the fetch instruction includes a multi-flow instruction which is divided into divided instructions and a single instruction. The instruction decoder includes: a pre-decoder including N number of slots each of which divides the multi-flow instruction into divided instructions; a main decoder including N number of slots each of which decodes the instructions to issue an execution instruction; and a pre-decoder buffer including N?K number of slots each of which temporarily stores instructions in the pre-decoder. The instruction decoder repeats transferring the divided instructions and the single instructions from the slots of the pre-decoder and the slots of the pre-decoder buffer to the main decoder as much as possible in order.Type: GrantFiled: February 4, 2019Date of Patent: February 15, 2022Assignee: FUJITSU LIMITEDInventors: Ryohei Okazaki, Yasunobu Akizuki
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Patent number: 11243778Abstract: The present disclosure relates to instruction dispatch mechanisms for superscalar processors having a plurality of functional units for executing operations simultaneously. Each particular functional unit of the plurality of functional units may be configured to output a capability vector indicating a set of operations that the particular functional unit is currently available to perform. As instructions are received in an issue queue, the functional unit to execute the instruction is selected by comparing capabilities required by the instruction to the asserted capabilities of each of the functional units. A functional unit may reset or de-assert a particular functionality while performing an operation and then re-assert the capability when the instruction is completed. A result of the operation may be stored in a skid buffer for at least as long as the chain execution time in order to avoid resource hazards are a write port of the vector register file.Type: GrantFiled: December 31, 2020Date of Patent: February 8, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Skand Hurkat, Jeremy Fowers
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Patent number: 11226821Abstract: A computer processor is provided that employs a plurality of operand storage elements that store operand data values and associated meta-data as unitary operand data elements as well as at least one functional unit that performs operations that produce and access the unitary operand data elements stored in the plurality of operand storage elements. The meta-data associated with a given operand data value as part of a unitary operand data element can specify type of the unitary operand data element (e.g., vector or scalar), elemental width and floating-point error flags. The meta-data can also be used to define special operand data values (e.g., Not-a-Result and None). The meta-data is useful in optimizing execution, such as in speculation and vectorized SIMD operations. The computer processor can also support a number of particular vector operations that are useful in optimizing execution of vectorized SIMD operations.Type: GrantFiled: September 10, 2019Date of Patent: January 18, 2022Assignee: Mill Computing, Inc.Inventors: Roger Rawson Godard, Arthur David Kahlich, David Arthur Yost, Sebastien Paul Maurice Mirolo
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Patent number: 11210103Abstract: A processor includes a plurality of execution units. At least one of the execution units is configured to determine, based on a field of a first instruction, a number of additional instructions to execute in conjunction with the first instruction and prior to execution of the first instruction.Type: GrantFiled: September 14, 2016Date of Patent: December 28, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Horst Diewald, Johann Zipperer
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Patent number: 11210105Abstract: A system to support data gathering for a machine learning (ML) operation comprises a memory unit configured to maintain data for the ML operation in a plurality of memory blocks each accessible via a memory address. The system further comprises an inference engine comprising a plurality of processing tiles each comprising one or more of an on-chip memory (OCM) configured to load and maintain data for local access by components in the processing tile. The system also comprises a core configured to program components of the processing tiles of the inference engine according to an instruction set architecture (ISA) and a data streaming engine configured to stream data between the memory unit and the OCMs of the processing tiles of the inference engine wherein data streaming engine is configured to perform a data gathering operation via a single data gathering instruction of the ISA at the same time.Type: GrantFiled: November 2, 2020Date of Patent: December 28, 2021Assignee: Marvell Asia Pte, Ltd.Inventor: Avinash Sodani
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Patent number: 11200059Abstract: A processor includes: an instruction fetch portion configured to fetch simultaneously a plurality of fixed-length instructions in accordance with a program counter; an instruction predecoder configured to predecode specific fields in a part of the plurality of fixed-length instructions; and a program counter management portion configured to control an increment of the program counter in accordance with a result of the predecoding.Type: GrantFiled: June 2, 2017Date of Patent: December 14, 2021Assignee: SONY CORPORATIONInventors: Hirokazu Hanaki, Satoshi Takashima
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Patent number: 11188340Abstract: Techniques for parallel execution of instructions in an instruction set are described. The techniques include determining a plurality of instruction streams and paths for a branch in an instruction set and executing the determined paths in parallel such that a mis-predicted path does not cause significant mis-prediction penalties.Type: GrantFiled: December 20, 2018Date of Patent: November 30, 2021Assignee: International Business Machines CorporationInventors: Brian W. Thompto, Hung Q. Le, Dung Q. Nguyen
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Patent number: 11183225Abstract: Memories and methods for performing an atomic memory operation are disclosed, including a memory having a memory store, operation logic, and a command decoder. Operation logic can be configured to receive data and perform operations thereon in accordance with internal control signals. A command decoder can be configured to receive command packets having at least a memory command portion in which a memory command is provided and data configuration portion in which configuration information related to data associated with a command packet is provided. The command decoder is further configured to generate a command control signal based at least in part on the memory command and further configured to generate control signal based at least in part on the configuration information.Type: GrantFiled: July 16, 2018Date of Patent: November 23, 2021Assignee: Micron Technology, Inc.Inventor: David Resnick
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Patent number: 11182160Abstract: A method and circuit for a data processing system provide a hardware accelerator repeat control instruction (402A) which is executed with a hardware accelerator instruction (402B) to extract and latch repeat parameters from the hardware accelerator repeat control instruction, such as a repeat count value (RPT_CNT), a source address offset value (ADDR_INCR0), and a destination address offset value (ADDR_INCR1), and to generate a command to the hardware accelerator (205) to execute the hardware accelerator instruction a specified plurality of times based on instruction parameters from the hardware accelerator instruction by using the repeat count value to track how many times the hardware accelerator instruction is executed and by automatically generating, at each execution of the hardware accelerator instruction, additional source and destination addresses for the hardware accelerator from the repeat parameters until the hardware accelerator instruction has been executed the specified plurality of times by theType: GrantFiled: November 24, 2020Date of Patent: November 23, 2021Assignee: NXP USA, Inc.Inventors: Maik Brett, Christian Tuschen, Sidhartha Taneja, Tejbal Prasad, Saurabh Arora, Anurag Jain, Pranshu Agrawal, Mukul Aggarwal, Ajay Sharma
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Patent number: 11182165Abstract: A system includes a branch predictor and a processing circuit configured to perform a plurality of operations including storing a skip-over offset value in the branch predictor. The skip-over offset value defines a number of search addresses of the branch predictor to be skipped. The operations further include searching the branch predictor for a branch prediction. Responsive to finding the branch prediction, the searching of the branch predictor is re-indexed based on the skip-over offset value associated with the branch prediction.Type: GrantFiled: November 19, 2018Date of Patent: November 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Bonanno, Daniel Lipetz, Brian Robert Prasky, Anthony Saporito, Adam Collura, Steven J. Hnatko