Abstract: An up/down counter device includes a D-type flip-flop circuit for producing a count signal of the 0th bit in synchronism with a clock signal, and 1st to n-th flip-flop circuits for producing count signals of the 1st to the n-th bits in synchronism with a clock signal. The first logic circuit is connected between the output of the D-type flip-flop circuit and the JK terminals of the first flip-flop circuit. The first stage logic circuit includes a first logic circuit section supplied with an up/down mode signal and the output signal of the D-type flip-flop circuit, and a second logic circuit connected in series with with the first logic circuit. Each of the 2nd to the n-th stage logic circuits includes a first logic circuit which is connected between the output terminal of the prestage flip-flop circuit and the JK terminals of the post stage flip-flop circuit, and a second logic circuit section connected to the first logic circuit.

Abstract: A device for measuring the rate of change of speed of a machine such as a turbine engine which includes a digital counter for counting a speed signal having a frequency proportional to engine speed for a predetermined period of time and decrementing said count for a second period of time with the counting periods being proportional to engine speed. The up and down counts are derived by dividing a fixed frequency clock signal by a number proportional to engine speed to generate a variable frequency signal which frequency is proportional to engine speed. The difference between the up and down counts generates a remainder signal which is compared to predetermined limits.

Abstract: A monitoring system for verifying that an input signal is toggling at a minimum frequency includes an edge detector to provide an output signal in response to a transition in the state of an input signal. The output signal is used to reset a resettable clock. In the event that the output signal is not received during a first reset period a first signal is generated and if there is no output within a second succeeding reset period, a second signal is generated.

Abstract: A shift register stage (20) for LSI and VLSI circuits is disclosed and includes a first latching circuit (21) responsive to a data input and for providing a first data output; control circuitry (23) responsive to the first data output and to a parallel data input for providing as a controlled data output a replica of the first data output or a replica of the parallel data input as a function of a control signal; a second latching circuit (25) responsive to the controlled data output and for providing a second data output; and a third latching circuit (27) responsive to the second data output and for providing a third data output. Also disclosed is a shift register (30) for LSI and VLSI circuits which advantageously utilizes the foregoing shift register stage of the invention and which provides for AC or delay testing of an integrated circuit which includes two of such shift registers (30, 60) and a logic network (50) interposed therebetween.

Abstract: A frequency divider for converting an n-bit periodic counting stream (each period containing a single zero or one bit, respectively, followed by n-1 one or zero bits) into a 2n-bit counting stream includes a two-input NOR gate or NAND gate, respectively, connected for delivering its output to an n-bit delay device, the NOR or NAND gate further connected for receiving the output of the delay device as feedback at one of its two-input terminals and for receiving the n-bit counting stream at the other of its two-input terminals. The output of the delay device is then a 2n-bit counting stream.

Abstract: The present invention enables improved response time in a linked cell discharge detection device by providing additional discharge paths when indicated to speed discharge of circuit nodes in a plurality of detection cells. A circuit node is periodically precharged by connection to a voltage source. This node is selectively discharged in accordance with at least one input signal. An output device connected to the circuit node generates an output indicative of the state of the charge on the circuit node. An additional discharge device which is responsive to the output device provides an additional discharge path when the output signal indicates a charge on the circuit node less than a predetermined magnitude. This additional discharge path speeds up the complete discharge of the circuit node.

Abstract: Charge transfer devices typically include a periodically reset floating element output stage coupled to an FET amplifier for sensing the transferred charges. For reducing both low-frequency l/f noise and high-frequency reset noise, the duty factor of the device clocking signals and the reset signal are picked so that at a selected multiple of the clock signal repetition rate, the information component is in phase quadrature with the reset noise component. The charge transfer device output signal is then synchronously detected with a reference signal which is in phase with the selected multiple of the information component.

Abstract: A device for generating clock signals at different frequencies and in particular a fractional frequency of a reference frequency comprises a reference frequency generator which delivers at the output a reference signal having a frequency f, a frequency-divider for dividing by an integer p which delivers a signal at the frequency f/p at the output, and a digital inverter for extracting the harmonic frequency of order n and delivering a signal at a multiple frequency in order to obtain at the output of the device a signal of digital type having the frequency n/pf. A feedback loop impedance is coupled to the input and output of the inverter and preferably has a maximum value at the frequency nf. A load impedance is coupled to the input of the inverter and preferably has a minimum value at the frequency nf.

Abstract: The present invention performs analog to digital conversion using the system clock of a microprocessor, the system clock being the clock which controls the rate of operation of the microprocessor. A varying analog signal is applied to the clock frequency control input of the microprocessor, thereby causing the clock frequency and the rate of operation of the microprocessor to vary in accordance with the varying analog signal. The clock is counted for a predetermined period of time. In the preferred embodiment this predetermined period of time is set by the 60 Hz AC power line. The counted contents at the end of this predetermined period of time is a digital representation of the varying analog signal. The microprocessor includes circuits for performing other operations at the rate set by the clock frequency. The other operations performed by the microprocessor must not be deleteriously affected by the varying rate of operation caused by the varying analog signal.

Abstract: A method of operating a solid state photodetector device which has N photodetectors formed on a first substrate portion connected to a readout stage, through a transition zone having at least one storage zone and a transfer gate, and a multiplexer of the charges transfer type which are on a second substrate portion. The second substrate portion is biased to a voltage which is negative with respect to that of the first substrate portion. Then, after integration of the charges from the photodetectors and tansfer thereof into the multiplexer in the usual way by leaving a charge Qo in the storage zone, the transfer gate is biased so that the voltage under this gate is less than the biasing voltage of the first substrate portion. Then the gate in the storage zone is biased so that the potential under this gate is between the bias voltage of the first substrate portion and the potential under the transfer gate so as to remove the charge Qo.

Abstract: The use of a comparator and counter associated, on-chip, with each photo-element of an array. Sensing each photo-element without discharging it and allowing each photo-element to accumulate a charge which is large relative to noise variations. These features result in a photo-detector with large signal-to-noise ratios.

Abstract: Disclosed is an apparatus for synchronizing a first signal with a second signal comprising a plurality of delay means D.sub.i as i goes from 1 to N, where N is an integer, each delay means D.sub.i having an input I.sub.i and a delay output O.sub.i for delaying a signal received at the respective input I.sub.i by an increment .delta.t of time in supplying the delayed signal at the respective delay output O.sub.i. The first delay means D.sub.1 of the plurality of delay means is connected to receive the first signal at its input I.sub.1. Each of the other delay means D.sub.i, for i equal to 2 to N, are connected in series such that the respective input I.sub.i is connected to receive the delay output O.sub.i-1 of the preceding delay means D.sub.i-1. A plurality of latch means L.sub.i, as i goes from 1 to N, are connected to be clocked by the second signal. Each of the latch means L.sub.i latches the signal at the delay output O.sub. i respectively for each of the delay means D.sub.

Abstract: A technique for compensating for charge transfer inefficiency in charge coupled devices. A convolver output is summed concurrently with a previous convolver output delayed by a sample period and weighted by a selected coefficient related to the charge transfer inefficiency.

Abstract: A power-saving serial data transfer circuit for outputting an inputted digital data signal through a plurality of serially connected shift register cells comprises n (=m.times.k) cells in k groups each containing m serially connected cells. A digital data signal is applied commonly to the first-stage cells of the groups and inputted in a time-wise segmented sequence to the cells by shift pulses with different phases. The inputted data signal is shifted through the cells within the same groups and is inputted to the last-stage cells of the groups. The inputted data signal is also outputted through a multiplexer connected to the last stage cells.

Abstract: A noise elimination circuit for eliminating noise signals from data given by a binary form includes a modulo in up/down counter having a first input for receiving binary data, a second input for receiving clock pulses and output for producing a counted signal. The counter is effected to count up in response to the clock pulses when the binary data is a HIGH, and to count down in response to said clock pulses when the binary data is a LOW. A decoder is provided which has inputs for receiving the counted signal, a first output for producing an indication signal when the counted signal corresponds to a first predetermined number i, and a second output for producing an indication signal when the counted signal corresponds to a second predetermined number j, in which i is equal to or greater than zero, j is greater than i and n is equal to or greater than j.

Abstract: A logic circuit that has a plurality of stages that are driven by a clock source that provides at least 2 clock signals and includes at least a single latch stage located between two of the plurality of stages is configured with field effect transistor technology. The latch stage includes an isolation means for isolating the preceding circuit of the plurality of stages from flow-through of the clocks and signals that are connected to the latch stage, and a latch circuit for storing the data that is applied to the latch stage between clock pulses. A plurality of latch stages can easily be configured as a shift register latch.

Abstract: A sinusoidal signal frequency multiplier, including a means for stabilizing the static input-ouput phase relationship. The static phase stabilizer compares the phase relationship between the frequency-multiplied output and the input signals, producing a signal which appropriately controls a phase shifter. This phase shifter operates on the input signal, the result serving as input to the frequency multiplier.

Abstract: A circuit for producing a pair of output pulses for each cycle of differentially applied input pulses includes a pair of input transistors to which the differential input pulses are applied and a pair of output transistors the collectors of which are connected to an output of the pulse doubling circuit and the bases of which are respectively coupled to the emitters of a corresponding input transistor. A pair of delay circuits are provided coupled respectively from one of the input transistors to the base of the opposite output transistor.

Abstract: A device for generating timing pulses for a rotary printing machine includes generators for generating synchronizing pulses and a pulse sequence corresponding to increments of angle of rotation of the machine. A pulse processing circuit includes address counters connected to the pulse generating means and being preset by an address presetting device. The output of the one address counter is connected to a PROM storing predetermined sequences of timing pulses. In order to provide for shifting of the stored timing pulse sequences in a negative direction, an inverting member is connected in the data bus between the rotary speed counter and the address presetting device of the one address counter. The inverting member can include either negators or storing means programmed with complementary values.

Abstract: A charge coupled device (CCD) analog shift register in a two-channel serial-parallel-serial (SPS) structure operating in a fast-in/slow-out (FISO) mode for high speed signal acquisition and temporary storage of a plurality of samples. The two CCD arrays are clocked simultaneously, and the input analog signal is demultiplexed to the two arrays. Additional transfer electrodes are provided at the input of one of the arrays, and the other array is provided with a sampling clock which is 180.degree. out of phase with the sampling clock of the first array; two consecutive samples of the input signal are taken during each transfer clock cycle. All signal samples are clocked through the arrays simultaneously and appear at the output at the same time.