Abstract: An integrated D flip-flop circuit including a plurality of inverter gates produces an output signal having a frequency that is equal to the frequency of an applied alternating input signal divided by a predetermined divide ratio wherein the improvement comprises an additional inverter gate that has an output connected to a predetermined one of the interconnected inverter gates and is responsive to a divide inhibit signal being applied to an input thereof for changing the divide ratio of the D flip-flop circuit.

Abstract: A parallel plate waveguide microwave antenna is presented in which transmission or reception of microwave energy is effected by radiating waveguide slots or apertures in a metallized glass plate or plate of other rigid dielectric material. The metallized glass plate cooperates with another metallized glass plate or other rigid dielectric material or a metal plate to define a parallel plate waveguide with air or an inert gas or vacuum as the dielectric between the plates. When used as a transmitter antenna, a central electrode propagates waves in the dielectric medium in expanding circles; and the slots or apertures in the metal layer act as scattering sites to couple the waves to free space. When used as a receiver antenna, the reverse will occur.

Abstract: There is disclosed a digital enhancement circuit which responds to the complementary inductance provided by a planar coil sensor which inductance varies in a complementary manner according to the position of a movable member associated with the planar coil configuration. The complementary inductance is coupled to an oscillator whereby the period of the oscillator is varied in a first mode according to a first inductance value and in a second mode according to a second inductance value. These signals are then processed by means of digital processing circuitry to develop a signal indicative of the difference of the periods as divided by the sum of the periods. This signal is a ratiometric signal, and by employing digital counters, one can provide an output signal having a predetermined gain factor and having the above noted ratiometric characteristic which signal is indicative of the position of the movable member as further enhanced by the gain factor.

Abstract: A means to set spark timing in accordance with engine speed includes a counter to count clock pulses between engine speed reference pulses. A read-only memory has successive memory locations each storing an addend quantity and a repeats number. An adder unit, including an accumulator, operates to access the memory locations, and to add the addend quantities to the contents of the accumulator repeatedly a number of times equal to the respective repeats numbers. A comparator produces an ignition firing pulse when the contents of the accumulator corresponds with the reference period number provided by the counter.

Abstract: A microstrip antenna is presented in which the circuit pattern is on the inner side of a glass plate and is spaced from the ground plane by an air dielectric. The outer side of the glass plate serves as a protective cover for the circuit pattern and the ground plane.

Abstract: A color image processing system is described which provides more realistic hard copy color images from composite video system input signals than previously available. The analog video information is converted to digital form by an analog-to-digital converter. The converter operates under control of a time base generator (100). The time base generator (100) provides more accurate control over the converter than the system clock signal. The generator (100) receives pulses from the synchronization separator, and following a programmable time delay supplies a control pulse to the converter to cause it to sample the analog waveform and convert it to digital format. The generator (100) employs a delay line (300) to detect the fraction of a system clock period between the sync pulse and the next clock pulse. The specified number of clock pulses are allowed to elapse. Then the delay line (300) is used to provide the necessary further delay.

Abstract: A digital sample rate reduction apparatus receives an input signal occurring at a given sample rate and produces an output signal occurring at a rate which is two-thirds the input sample rate. One half of the output samples are interpolated samples and the other half are original input samples.

Abstract: A horn antenna suitable for an amplitude-comparison broadband direction-finding system with 360.degree. azimuth coverage comprises a horn with a wide angle of flare in a plane normal to the z-axis of a cylindrical co-ordinate system and an aperture which is suitably cylindrical, as seen from that axis, and further comprises means for launching electromagnetic energy into the horn towards the aperture. In order to provide a substantially constant beamwidth over a broad frequency range, which may be as wide as 7:1, the horn and launching means are adapted to launch and propagate to the aperture a substantially pure lowest order circumferential mode having its electric field in a direction parallel to the z-axis, the launching means acting substantially as a line source coincident with the z-axis. The flare angle may be 180 degrees, and the launching means may comprise an electric probe extending substantially along the z-axis.

Abstract: A microprocessor transfers into a first so-called "fixed" zone of the memory the intermediate total distance travelled since the vehicle was put on the road and, in a second so called "journey" zone of the memory the successive partial distances travelled between each power supply cut off, the successive partial distances being transferred into the cells of the journey zone of the memory each time the power is switched off.

Abstract: A bidirectional shift register includes a plurality of serially connected cells with each cell having a first circuit portion and a second circuit portion. Each circuit portion includes at least two parallel inverters connected in opposite directions. The relative transconductance of the oppositely connected inverters in each circuit portion of a cell can be varied thereby determining the direction of data flow through the circuit portion and through the bidirectional shift register.

Abstract: An up/down counter interface converts input information suitable for the operation of one type up/down counter, which type receives input information in the form of a direct current logic signal indicating direction and a train of electric pulses representing increments of information, to input information suitable for the operation of a second type up/down counter, which second type receives input information in the form of two identical pulse trains representing increments of information, direction being determined by the relative displacement in time of the two pulse trains.

Abstract: A driving time alarm for a vehicle comprises a recess time setting counter for counting clock pulses during the time when the vehicle is not under running; and a driving time limit setting counter which counts during the time when said vehicle is under running and is reset by the count-up of said recess time setting counter, whereby an alarm is given when said driving time limit setting counter comes to a count-up state.

Abstract: A detector circuit for detecting a phase or frequency error of an input signal. One mode of at least two detection modes is selected according to a phase or a frequency of the input signal with each mode having a reference value of a phase or a frequency of the input signal and reference values of the detection modes being different from each other. A pulse signal having a phase corresponding to a difference between an actual phase or frequency of the input signal and the reference value of the phase or the frequency is generated, and a predetermined carrier signal is pulse width modulated with a predetermined modulation factor in response to the pulse signal, the modulation factor being different for each detection mode.

Abstract: An apparatus having a charge coupled device which is used as a solid state type image pickup apparatus and prior to inversion of the level of drive pulses supplied to two electrode groups from among a plurality of electrode groups of a CCD, each electrode group is disconnected once electrically from each drive pulse generating circuit, in which period two electrode groups whose level of drive pulse are inverted are electrically short-circuited, whereby all the charges in capacitors formed between the electrodes and a substrate are not discharged but about half of the charges can be reused for charging another capacitor which is formed between the electrodes and the substrate and is to be charged next, thus enabling a saving of power consumption, a reduction of heat dissipation losses, and enabling the miniaturization of the image pickup apparatus using a charge coupled device.

Abstract: A frequency conversion interface is disposed between the main and subreflectors in a multiple beam antenna system so that the antenna system amplification factor will be defined by m=(f.sub.1 /f.sub.2).multidot.(.omega..sub.1 /.omega..sub.2), to permit large main reflector to subreflector area ratios while maintaining small amplification factors.

Abstract: A first circuit branch subjected to an input voltage and including a first resistance and a second circuit branch subjected to a reference voltage and including a second resistance are connected to a coupling circuit, which is responsive to the current circulating in the first branch to cause a current of the same value to circulate in the second branch. An output voltage taken at a point between said coupling circuit and said second resistance constitutes the modified signal.

Abstract: When the frequency dividing ratio of a programmable divider in a phase locked loop is controlled by an up/down counter, the designing of a system can be simplified by reducing the number of control lines connected to a microprocessor as much as possible. An up/down counter control circuit of the present invention comprises a timing control means to which a latch signal, a data and a clock signal are supplied, a data memory means and an up/down counter and is characterized in that under the control of the timing control means, in the data latch mode, a first level (0 or 1) of the latch signal is detected and in synchronism with the clock signal that data is latched in the data memory means, while in the up/down mode, a second level (1 or 0) of the latch signal is detected and the content of the up/down counter is changed in response to the level of the data synchronized with the clock signal.

Abstract: The invention provides a conversation device having a space key for instructing feeding of a printing tape without printing, a pulse oscillator for producing pulses of predetermined period upon depression of the space key, a counter for counting the pulses generated from the pulse oscillator, a one-shot multivibrator for producing a pulse to indicate that the count value has reached a predetermined value, a flip-flop which is set by the pulse from the one-shot multivibrator and allows the pulses from the pulse oscillator to be supplied to a motor driver for amplifying the pulses and which is reset when the predetermined number of pulses from the pulse oscillator is received and prohibits the supply of the pulse oscillator to the motor driver, and a pulse motor for feeding the printing tape without printing. Therefore, when the flip-flop is set, the motor driver causes the pulse motor to drive the printing tape for a predetermined length corresponding to a plurality of characters.

Abstract: A signal transition detection circuit detects a transition which satisfies predetermined criteria related to magnitude and time. These criteria include that the magnitude of a group of signal samples preceeding the transition and a group thereof following the transition each be relatively close in magnitude and that the difference between the magnitudes of signal samples preceeding and following the transition be at least a predetermined amount. Further, detection criteria are included to test for smoothness and monotonicity of the transition and to exclude detection of transitions having magnitude changes exceeding a predetermined amount.

Abstract: A plurality of cascaded RS flip-flops are enabled by gating circuitry coupled between the output of the last RS flip-flop of the cascaded RS flip-flops and the set and reset inputs of the RS flip-flops to enable digital data stored in a preceding or following RS flip-flop to be shifted into an adjacent following or preceding RS flip-flop upon successive occurrences of complementary clocking pulses applied to the gating circuitry.