Abstract: Techniques disclosed herein, provide a method and fabrication structure for accurately increasing feature density for creating high-resolution features and also for cutting on pitch of sub-resolution features. Techniques include using multiple materials having different etch characteristics to selectively etch features and create cuts or blocks where specified. A multiline layer is formed of three or more different materials that provide differing etch characteristics. Etch masks, including interwoven etch masks, are used to selectively etch cuts within selected, exposed materials. Structures can then be cut and formed. Forming structures and cuts can be recorded in a memorization layer, which can also be used as an etch mask.

Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).

Abstract: Wavelength converters, including polarization-enhanced carrier capture converters, for solid state lighting devices, and associated systems and methods are disclosed. A solid state radiative semiconductor structure in accordance with a particular embodiment includes a first region having a first value of a material characteristic and being positioned to receive radiation at a first wavelength. The structure can further include a second region positioned adjacent to the first region to emit radiation at a second wavelength different than the first wavelength. The second region has a second value of the material characteristic that is different than the first value, with the first and second values of the characteristic forming a potential gradient to drive electrons, holes, or both electrons and holes in the radiative structure from the first region to the second region. In a further particular embodiment, the material characteristic includes material polarization.

Abstract: A method of fabricating a three-dimensional semiconductor device is provided. The method includes providing a substrate with a peripheral circuit region and a cell array region; forming a peripheral structure on the peripheral circuit region, and forming an electrode structure on the cell array region. The electrode structure includes a lower electrode, a lower insulating planarized layer on the lower electrode, and upper electrodes and upper insulating layers vertically and alternatingly stacked on the lower insulating planarized layer, and the lower insulating planarized layer may be extended to cover the peripheral structure on the peripheral circuit region. An upper insulating planarized layer is formed to cover the electrode structure and the lower insulating planarized layer on the peripheral circuit region.

Abstract: One embodiment is a semiconductor device including: at least one patterned dielectric layer having at least one opening therein, said at least one opening having sidewalls and bottom; at least one barrier layer disposed over the sidewalls and bottom; a first metallic layer disposed over the at least one barrier layer; a second metallic layer disposed over the first metallic layer; and a metallic filling layer disposed over the second metallic layer; wherein: the first metallic layer is continuous over the sidewalls and bottom, has a thickness in a range from about 10 ? to no more than 40 ? over a sidewall of the at least one opening; and the second metallic layer, and the metallic filling layer are selected from a group consisting of Cu, Ag, and alloys containing one or more of these metals.

Abstract: Disclosed are a light emitting device and a light emitting device package. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer, an adhesive layer contacting a top surface of the first conductive semiconductor layer, a first electrode contacting a top surface of the first conductive semiconductor and a top surface of the adhesive layer, and a second electrode contacting the second conductive semiconductor layer, wherein the adhesive layer contacting the first electrode is spaced apart from the second electrode.

Abstract: A method of manufacturing a semiconductor device includes forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing: supplying a precursor containing a predetermined element to the substrate in a process chamber, removing the precursor from the process chamber, supplying a first reactant containing nitrogen, carbon and hydrogen to the substrate, removing the first reactant from the process chamber, supplying a second reactant containing oxygen to the substrate, and removing the second reactant from the process chamber. A time period of the act of removing the precursor is set to be longer than a time period of the act of removing the first reactant, or a time period of the act of removing the second reactant is set to be longer than the time period of the act of removing the first reactant.

Abstract: A method of manufacturing a semiconductor device includes: implanting charged particles into a first range and a second range in a semiconductor substrate from at least one of a first surface of the semiconductor substrate and a second surface of the semiconductor substrate located on an opposite side of the first surface so as to increase crystal defect densities in the first range and the second range; implanting n-type impurities into the first range from the first surface so as to make a region amorphous, the region being in the first range and disposed at the first surface; irradiating the first surface with first laser after the implantation of the charged particles and the implantation of the n-type impurities so as to heat the first range and the second range; and crystallizing the region which has been made amorphous in or after the irradiation of the first laser.

Abstract: Methods are described for reducing the wet etch rate of dielectric films formed on a patterned substrate by flowing the material into gaps during deposition. Films deposited in this manner may initially exhibit elevated wet etch rates. The dielectric films are treated by exposing the patterned substrate to a high pressure of water vapor in the gas phase. The treatment may reduce the wet etch rate of the dielectric films, especially the gapfill portion of the dielectric film. Scanning electron microscopy has confirmed that the quantity and/or size of pores is reduced or eliminated by the procedures described herein. The treatment has also been found to reduce the etch rate, e.g., at the bottom of gaps filled with the dielectric film.

Abstract: Methods of lithographic patterning. A metal hardmask layer is formed on a dielectric layer and a patterned layer is formed on the metal hardmask layer. A metal layer is formed on an area of the metal hardmask layer exposed by an opening in the patterned layer. After the metal layer is formed, the patterned layer is removed from the metal hardmask layer. After the patterned layer is removed, the metal hardmask layer is patterned with the metal layer masking the metal hardmask layer over the area.

Abstract: A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework. A bottom wafer is placed on a bottom bonding framework that includes a plurality of inlet holes around a periphery of the bottom bonding framework. The top bonding framework is in overlapping relation to the bottom bonding framework such that a gap exist between the top wafer and the bottom wafer. A gas stream is circulated through the gap between the top wafer and the bottom wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the top wafer and the bottom wafer.

Abstract: According to various embodiments, a method may include: providing a substrate having a first side and a second side opposite the first side; forming a buried layer at least one of in or over the substrate by processing the first side of the substrate; thinning the substrate from the second side of the substrate, wherein the buried layer includes a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer.

Abstract: A device is disclosed. The device includes a baseboard including a first set of metallic contact pads, a semiconductor integrated chip (IC) package including a second set of metallic contact pads and metallic interconnects to connect the first set of metallic contacts pads and the second set of metallic contact pads through metallic interconnects. The second set of metallic contact pads includes a first group of contact pads and a second group of contact pads. The first group of contact pads are designed to carry a high frequency signal. The baseboard includes a plurality of holes that at least partially segregates a first group of metallic interconnects that connects the first group of contact pads to the baseboard and a second group of metallic interconnects that connects the second group of contact pads to the baseboard.

Abstract: A display system is disclosed. The display system comprises a light emitting diode (LED) device and a backplane (BP) device. The LED device comprises a plurality of LEDs having LED terminals. An LED bonding surface comprising a dielectric layer with LED bonding surface contact pads is coupled to diode terminals of the LEDs. The backplane (BP) device comprises a BP substrate having top and bottom surfaces. A plurality of system on chip (SoC) chips are bonded to chip pads disposed on a bottom surface of the BP device. The SoC chips are electrically coupled to the CMOS components of the BP device and LEDs of the LED device.

Abstract: Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.

Abstract: Methods and apparatus are described for creating a multi-die package from a wafer without dicing the wafer into individual dies and reassembling the dies on an interposer. One example method generally includes testing a plurality of IC dies disposed on a wafer; disposing one or more connectivity layers above the plurality of IC dies, the one or more connectivity layers comprising one or more electrical conductors configured to connect together two or more of the plurality of dies in each of one or more groups of the IC dies; dicing the wafer having the one or more connectivity layers disposed above the plurality of dies into sets, each set comprising one or more of the plurality of dies, wherein the dicing is based on the one or more groups having IC dies that passed the testing; and packaging at least a portion of the sets of dies.

Abstract: A method of fabricating a solar cell array on the surface of a support by providing an assembly fixture having a smooth, concave surface; mounting a film composed of ethylene tetrafluoroethylene (ETFE) directly on the surface of the fixture; mounting a film composed of a non-crosslinked silicone pressure sensitive adhesive directly over the ETFE film; mounting an array of interconnected solar cells directly over the adhesive film. An uncured supporting film composed of a composite material is mounted directly on the back side of the solar cells; and the film of composite material is co-cured so that the array of interconnected solar cells is bonded to the supporting film. The bonded and cured film of composite material and an array of interconnected solar cells with the ETFE film is then removed from the assembly fixture.

Abstract: A method of forming a charge pattern on a microchip includes depositing a material on the surface of the microchip, and immersing the microchip in a fluid to develop charge in or on the material through interaction with the surrounding fluid.

Abstract: A method of manufacturing semiconductor device includes forming a plurality of sacrificial layers and a plurality of semiconductor layers repeatedly and alternately stacked on a substrate, partially removing the sacrificial layers, forming spacers in removed regions of the sacrificial layers, and replacing remaining portions of the sacrificial layers with a gate electrode. Each of the sacrificial layers includes first portions disposed adjacent to the plurality of semiconductor layers and a second portions disposed between the first portions. The second portion having a different composition from the first portions.

Abstract: An integrated circuit structure includes a first dielectric layer, an etch stop layer over the first dielectric layer, and a second dielectric layer over the etch stop layer. A via is disposed in the first dielectric layer and the etch stop layer. A metal line is disposed in the second dielectric layer, wherein the metal line is connected to the via. The etch stop layer includes a first portion having an edge contacting an edge of the via, wherein the first portion has a first chemical composition, and a second portion in contact with the first portion. The second portion is spaced apart from the via by the first portion, and wherein the second portion has a second chemical composition different from the first composition.