Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.

Abstract: A structure having fully aligned via connecting metal lines on different Mx levels. The structure may include a first metal line and a second metal line in a first ILD, a cap covering the first ILD, the second metal line and a portion of the first metal line, a second ILD on the cap, and a via that electrically connects the first metal line to a third metal line, wherein the third metal line is above the first metal line and runs perpendicular to the first metal line, the via is fully aligned to the first metal line and the third metal line, and the via electrically connects the first metal line to the third metal line.

Abstract: Uniaxially strained nanowire structures are described. For example, a semiconductor device includes a plurality of vertically stacked uniaxially strained nanowires disposed above a substrate. Each of the uniaxially strained nanowires includes a discrete channel region disposed in the uniaxially strained nanowire. The discrete channel region has a current flow direction along the direction of the uniaxial strain. Source and drain regions are disposed in the nanowire, on either side of the discrete channel region. A gate electrode stack completely surrounds the discrete channel regions.

Abstract: The present disclosure relates to an image sensor having autofocus function and associated methods. In some embodiments, the integrated circuit has a photodiode array with a plurality of photodiodes disposed within a semiconductor substrate and a composite grid overlying the photodiode array and having a first plurality of openings and a second plurality of openings extending vertically through the composite grid. The integrated circuit further has an image sensing pixel array with a plurality of color filters disposed in the first plurality of openings. The integrated circuit further has a phase detection pixel array having a plurality of phase detection components that are smaller than the plurality of color filters and that have a low refractive index (low-n) material with a refractive index (n) smaller than a refractive index of the plurality of color filters, wherein the phase detection components are disposed in the second plurality of openings.

Abstract: A method of making a semiconductor device includes patterning a fin in a substrate; forming a gate between source/drain regions over the substrate, the gate having a dielectric spacer along a sidewall; removing a portion of the dielectric spacer and filling with a metal oxide to form a spacer having a first spacer portion and a second spacer portion; forming a source/drain contact over at least one of the source/drain regions; recessing the source/drain contact and forming a via contact over the source/drain contact; and forming a gate contact over the gate, the gate contact having a first gate contact portion contacting the gate and a second gate contact portion positioned over the first gate contact portion; wherein the first spacer portion isolates the first gate contact portion from the source/drain contact, and the second spacer portion isolates the second gate contact portion from the source/drain contact.

Abstract: A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset spacer on a sidewall of the first gate stack; a stressor in the semiconductor substrate and adjacent to the first offset spacer; and a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor.

Abstract: A method for manufacturing a solid-state image pickup apparatus includes forming a first insulating film over a substrate after forming a gate electrode of a first transfer transistor and a gate electrode of a second transfer transistor, forming a second insulating film on the first insulating film, forming a first structure and a second structure on side surfaces of the gate electrodes of the first and second transfer transistors, respectively, via the first insulating film by etching the second insulating film in such a manner that the first insulating film remains on a semiconductor region of a photoelectric conversion unit and a semiconductor region of a charge holding unit, and forming a light shielding film that covers the gate electrode of the first transfer transistor, the semiconductor region of the charge holding unit, and the gate electrode of the second transfer transistor.

Abstract: A method for producing a rear-side contact system for a silicon thin-film solar cell having a pn junction formed from a silicon absorber layer and an emitter layer includes applying an organic insulation layer to the emitter layer; producing contact holes in the insulation layer as far as the absorber layer and the emitter layer; subsequently insulating the contact holes; subsequently applying a low-melting metal layer to form n and p contacts in the contact holes; separating the metal layer into n-contacting and p-contacting regions by laser-cutting; before applying the organic insulation layer to the emitter layer, applying a TCO layer; producing holes for contacts for the silicon absorber layer in the organic insulation; and subsequently selectively doping the produced holes for the contacts as far as the silicon absorber layer.

Abstract: A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned.

Abstract: A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, and a source region and a drain region formed in the substrate. The semiconductor device further includes an impurity diffusion stop layer formed in a recess of the substrate between the source region and the drain region, wherein the impurity diffusion stop layer covers bottom and sidewalls of the recess. The semiconductor device further includes a channel layer formed over the impurity diffusion stop layer and in the recess, and a gate stack formed over the channel layer.

Abstract: In a Cu wiring manufacturing method for manufacturing Cu wiring that fills a recess formed in a predetermined pattern on a surface of an interlayer insulating film of a substrate, a MnOx film that becomes a self-formed barrier film by reaction with the interlayer insulating film is formed at least on a surface of the recess by ALD. A CuOx film that becomes a liner film is formed on a surface of the MnOx film by CVD or ALD. An annealing process is performed on the substrate on which the CuOx film is formed and the CuOx film is reduced to a Cu film by oxidation-reduction reaction between the MnOx film and the CuOx film. A Cu-based film is formed on the Cu film obtained by reducing the CuOx film by PVD to fill the Cu-based film in the recess.

Abstract: A semiconductor device including a conductive element and an interface surface fabricated atop the conductive element, and a method for fabricating such a device are described. An exemplary device includes a substrate having a conductive element and a metal layer fabricated atop the conductive element. An oxide layer is fabricated atop the metal layer, thus forming an interface surface. During polishing (e.g., planarization), in which an upper portion of the interface surface is removed, the presence of the interface surface greatly reduces the loading on the conductive element. A second substrate fabricated using the same process may be stacked atop the first substrate and bonded using a hybrid bonding process.

Abstract: A method for manufacturing a semiconductor device in accordance with the present invention includes the steps of preparing a semiconductor substrate, placing the semiconductor substrate on an electrostatic chuck, chucking the semiconductor substrate after raising a temperature of the electrostatic chuck to a first temperature, raising a temperature of the electrostatic chuck to a second temperature which is higher than the above-described first temperature in a state where the semiconductor substrate is chucked, and performing a treatment to the semiconductor substrate in a state where a temperature of the electrostatic chuck is maintained at the above-described second temperature.

Abstract: A manufacturing method of a TFT substrate structure is provided, in which a graphene layer is formed on a semiconductor layer and after the formation of a second metal layer, the second metal layer is used as a shielding mask to conduct injection of fluoride ions into the graphene layer to form a modified area in a portion of the graphene layer that is located on and corresponds to a channel zone of the semiconductor layer. The modified area of the graphene layer shows a property of electrical insulation and a property of blocking moisture/oxygen so as to provide protection to the channel zone. Portions of the graphene layer that are located under source and drain electrodes are not doped with ions and preserve the excellent electrical conduction property of graphene to provide electrical connection between the source and drain electrodes and the semiconductor layer.

Abstract: A magnetic junction and method for providing the magnetic junction are described. The magnetic junction resides on a substrate and is usable in a magnetic device. The magnetic junction includes free and pinned layers separated by a nonmagnetic spacer layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The free layer has a free layer perpendicular magnetic anisotropy energy greater than a free layer out-of-plane demagnetization energy. The free layer includes an alloy. The alloy includes [CoxFeyBz]uMgt, where u+t=1 and x+y+z=1.

Abstract: An integrated circuit comprises a first doped region and a second doped region in a substrate. The second doped region is separated from the first doped region by a first spacing. The integrated circuit further comprises a dielectric layer over the substrate and a gate over the dielectric layer. The gate is positioned having the first doped region on a first substrate side of the gate and the second doped region on a second substrate side of the gate opposite the first substrate side of the gate. The integrated circuit also comprises a third doped region in the substrate separated from the first doped region by a second spacing. The integrated circuit further comprises a fourth doped region in the substrate. The gate and the third doped region are coupled with a first voltage supply, and the fourth doped region is coupled with a second voltage supply.

Abstract: A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

Abstract: A method for producing an optoelectronic semiconductor chip is disclosed. In an embodiment, the method includes providing a semiconductor body with a pixel region including different subpixel regions, each subpixel region having a radiation exit face, applying an electrically conductive layer onto the radiation exit face of a subpixel region, wherein the electrically conductive layer is suitable at least in part for forming a salt with a protic reactant, and depositing a conversion layer on the electrically conductive layer using an electrophoresis process, wherein the deposited conversion layer comprises pores.

Abstract: A semiconductor device (100) comprises: a semiconductor substrate (1); a drift region (2) of a first conductivity type having a trench in part of an upper portion thereof and arranged on a first main surface of the semiconductor substrate (100); an electric field reducing region (4) of a second conductivity type arranged, in a bottom portion of the trench, only around a corner portion and not in a center portion; an anode electrode (9) embedded in the trench; and a cathode electrode (10) arranged on a second main surface of the semiconductor substrate (100) which is opposite to the first main surface.

Abstract: A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film.