Patents Examined by K Thangavelu
  • Patent number: 7383168
    Abstract: A method and system for element testing is described. A first module is generated and has at least one associated state. A second module is generated based on the first module. The second module is associated with a test element. The test element is controlled based on the second module and the states, and the test element is applied to a design-under-test. Data flow information, determined while applying the test element to the design-under-test, is store in a transaction database, and the data items read and modified by the data flow information are stored in a data database. At least one result is determined based on the application of the test element to the design-under-test.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: June 3, 2008
    Assignee: Fujitsu Limited
    Inventors: Rajarshi Mukherjee, Toshiya Mima, Yozo Nakayama
  • Patent number: 7369973
    Abstract: The disclosure is directed to a computer-implemented method of representing fluid flow in a physical fluid reservoir. The method includes generating a mesh representation of the physical fluid reservoir having a plurality of mesh elements. Each of the plurality of mesh elements is representative of a regional portion of the fluid reservoir. The method further includes generating a matrix-based representation of fluid flow comprising matrix elements associated with a mesh element and selectively weighting the matrix elements based on fluid flow direction in the regional portion of the fluid reservoir represented by the mesh element associated with the matrix element.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: May 6, 2008
    Assignee: Object Reservoir, Inc.
    Inventors: Stephen R. Kennon, Steven B. Ward
  • Patent number: 7366647
    Abstract: The LSI design and development in manufacture is actualized by algorithm design, architecture design, actual hardware and software design, and verification. Herein, the architecture design contains a simulation program structuring process and a bus performance evaluation process, which are interconnected by a feedback loop. In the algorithm design, sources are described by the general-purpose high-level language such as the C language and C++ language. In the simulation program structuring process, the sources are subjected to isolation of the hardware and software, while an evaluation function is created to count bus traffic of the bus interconnecting the hardware and software. Every time data is written to a pre-defined variable loaded onto the bus, the evaluation function is performed to modify the sources. Then, evaluation is performed on the performance of the bus, so that the bus traffic for its processing rate is finally produced.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: April 29, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Yasuteru Araya, Yuichi Maruyama
  • Patent number: 7356456
    Abstract: In a design system using virtual hardware models, a filtering manager for filtering execution results and determining which software instructions are candidates for restructuring. In some examples, illegal address range instructions are identified based on exception records and restructured software instructions may redirect memory access to an appropriate memory location thereby enabling the use of hardware device drivers in conjunction with hardware emulations, simulations or virtual models without requiring driver source code modifications. Using different filtering criteria, some or all legal and/or illegal memory access software instructions may be redirected to mapped memory locations enabling control over memory access functions. In some cases, debugging tools may be configured or altered to reduce, limit or disable exception handling trace messages, thereby improving overall processing performance by eliminating or reducing unnecessary or burdensome error or trace report generation.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: April 8, 2008
    Assignee: Paravirtual Corporation
    Inventor: Ross Wheeler
  • Patent number: 7356454
    Abstract: A method for emulating a logic circuit having at least one set of identical logic modules is disclosed. Each logic module in a set has logic elements and memory elements that store a module state of that logic module. The logic circuit is emulated by extracting a logic module from a set of identical logic modules, translating the extracted logic module for iterative representation of the module state of each of the logic modules with a single instance of the logic elements, and configuring a logic device with the translated logic module to emulate the logic circuit.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: April 8, 2008
    Assignee: UD Technology Corporation
    Inventors: Hirofumi Sakane, Levent Yakay, Vishal Karna, Clement Leung, Guang R. Gao
  • Patent number: 7353162
    Abstract: A method and a system provide a reconfigurable platform for designing and emulating a user design. The method and system facilitates design and emulation of a system-on-a-chip type user design. The netlist of a user design may be included with netlists from customized or optimized third party circuits in an emulation using a platform including a number of field programmable devices. Various customized circuits for specific development activities, such as debugging, performance analysis, and simulator linkage may be configured to interact with the user design.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: April 1, 2008
    Assignee: S2C, Inc.
    Inventors: Thomas B. Huang, Mon-Ren Chene
  • Patent number: 7353153
    Abstract: The present invention discloses a structural and mechanical model and modeling methods for human bone based on bone's hierarchical structure and on its hierarchical mechanical behavior. The model allows for the assessment of bone deformations, computation of strains and stresses due to the specific forces acting on bone during function, and contemplates forces that do or do not cause viscous effects and forces that cause either elastic or plastic bone deformation.
    Type: Grant
    Filed: May 11, 2004
    Date of Patent: April 1, 2008
    Inventors: Maria-Grazia Ascenzi, John M. Kabo
  • Patent number: 7349837
    Abstract: The system includes a novel software application interactive representation modeling language, a software application (82) operative to use the modeling language to create, read and modify interactive representation models of the proposed applications, a memory (86) to store requirement data and interactive representation model data, a software application (92) operative to read and update the interactive representation model data across a computer network, a software application (76) operative to maintain a record of the requirements and to administer operation of the system, a software application (78) operative to render interactive representations of the proposed applications in browser readable format, a software application (82) operative to allow multiple instances of other applications to access interactive representation data and requirement data residing in the memory and a software application (84) operative to allow an individual user's interactions with the system to be broadcast across a network
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: March 25, 2008
    Assignee: iRise
    Inventors: Maurice Martin, Stephen Brickley, Leon Amdour, Alex Kravets, Brian Fan, Dominic Infante, Stuart Larking, Paul Aldama
  • Patent number: 7340383
    Abstract: A conversion processing method, device and computer program product. The device includes a memory for storing drafting data, a selector for choosing the drafting data stored in the memory, a converter for converting the drafting data chosen by the selector into shape data, and a transmitter for transmitting the shape data to a browsing management server that stores the shape data and enables browsing the shape data via a communications network. The converter converts, from drafting data selected by the selector, the drafting data having a registration date and time corresponding to the date on which the converter has converted the drafting data, and that is also more recent than the registration date on which the drafting data is registered in the memory.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: March 4, 2008
    Assignee: Ricoh Company, Ltd.
    Inventors: Takane Mayuzumi, Hideki Tamura
  • Patent number: 7328141
    Abstract: A user interface for a traffic load simulator for a telecommunication system divides call traffic into sub-groups of call traffic that have a common characteristic. Such sub-groups may include rush hour callers, lunch time callers, teenagers, internet surfers, business customers and other background callers that do not fit into any one sub-group. Each sub-group is represented as a timeline on a display where the traffic for the sub-group is simulated with ramp up and decline rates corresponding to the rate at which calls are added to the system or disconnected from the system and steady state volume between the ramp up and decline, all as a function of time-of-day. The timelines may be manipulated by graphically changing the rates, steady state volume and time-of-day for the events. In this manner realistic traffic loads on the system may be simulated to determine times and nodes when and where the system may be overwhelmed.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: February 5, 2008
    Assignee: Tektronix, Inc.
    Inventor: Frederick A. Azinger
  • Patent number: 7324932
    Abstract: A method of and an apparatus for designing a test environment providing reliable test signal integrity, and of evaluating performance of the test environment and an electronic device during testing of the electronic device. A virtual test environment is created emulating an actual test environment in which the electronic device is to be tested. A virtual calibration of the virtual test environment may be performed, to more closely emulate the actual test environment. A virtual device emulating the actual electronic device is implanted into the virtual test environment, and that virtual device is stimulated with an input test signal emulating the actual input signal that is applied to the actual electronic device in the actual test environment. The integrity of the input test signal and the resulting output signal is evaluated.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: January 29, 2008
    Assignee: Intel Corporation
    Inventors: Sunil K. Jain, Gregory P. Chema
  • Patent number: 7324931
    Abstract: An automated model componentization feature systematically converts duplicate or otherwise amenable patterns in a model into references. Multiple references are simplified to one unit that contains the otherwise duplicated functionality. Duplicated or selected functionality is identified based on a number of arguments that may be user supplied. These arguments include the level of polymorphism (i.e., which of the sample times, dimensions, and data types can be propagated in) but also the maximum size of the patterns to look for to address the general trade-off of generating few partitions with many blocks or many partitions with few blocks and which modeling constructs are used (e.g., whether Go To/From connections such as in Simulink® are present). Model conversions can result in potentially disjoint partitions.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: January 29, 2008
    Assignee: The Mathworks, Inc.
    Inventor: Arwen Warlock
  • Patent number: 7321849
    Abstract: A system and process for providing a geometric model database for use in an ubiquitous computing environment. In general, the geometric model database system and process is capable of accepting information about the geometric state of the environment, building a geometric model of this environment, maintaining and storing the geometric model, and handling queries about the environment's geometric state. The task of building a geometric model begins by establishing a set of entities that are of interest in the environment. An entity represents an object which exists in the physical world. In the geometric model database, an entity is represented by a coordinate frame and an extent. Extents refer to the physical size, or some service region such as a field of view, associated with an entity. The location of an entity in the physical world is defined using “measurements”. In general, a measurement is simply a mathematical description of the geometric relationship between two entities.
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: January 22, 2008
    Assignee: Microsoft Corporation
    Inventors: Barrett Brumitt, Steven Shafer, Brian Meyers
  • Patent number: 7319945
    Abstract: The present invention relates to methods, computer systems, and computer programs for simulating a biological network. The methods of the present invention facilitate biological network simulations via automated equation generation based on the concept of a hierarchy of canonical forms that describe biological processes at various levels of detail. At each level of hierarchy two classes of canonical forms can be identified: the input canonical form, that is used to supply information to the program, and the output canonical form that is produced by a simulator. The methods in certain preferred embodiments include explicit output description and flexible user intervention at several steps through the model generation. Furthermore, preferred embodiments of the present invention provide the modeling of developmental networks using an organism-as-a-graph approach using domains and fields.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: January 15, 2008
    Assignee: California Institute of Technology
    Inventors: Bruce E. Shapiro, Eric D. Mjolsness, Andre Levchenko
  • Patent number: 7318012
    Abstract: An Adaptive, Any-Time Case Retrieval process combines existing knowledge (emergent clustering, case retrieval with CRN) in a novel and advantageous way. Although ideally suited to the Digital Body Development System (DBDS), the method is applicable to any problem solving environment involving iterative simulations. Given a description of a problem to be solved, a candidate solution is applied to generate a problem solving base case. The description of the problem is modified and the modification is recorded. Candidate solutions are applied to the problem as modified, thereby generating a problem solving event case. These steps are repeated so as to rank the relevance of the cases generated to arrive at an optimal solution to the problem. In the preferred embodiment a case retrieval network (CRN) structure is used in the ranking process.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: January 8, 2008
    Inventor: Sven Brueckner
  • Patent number: 7314491
    Abstract: This invention relates to the art of computer system emulation and, more particularly, to a computer system emulator in which the functions normally performed by the hardware in a legacy central processor unit are emulated by a software program. The invention is to enhance the emulated instruction set beyond that of the legacy machine such to include as new single instructions a method for invoking operating system functions, with the machine coding of the operating system functions now being performed by machine code native to the new host machine, rather than as a sequence of emulated legacy instructions.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: January 1, 2008
    Assignee: Bull HN Information Systems Inc.
    Inventors: Russell W. Guenthner, Rodney B. Schultz, F. Michel Brown, Stefan R. Bohult, William J Brophy
  • Patent number: 7302380
    Abstract: A simulation apparatus for simulating a pipeline processor including a pipeline simulation unit and an instruction simulation unit. The simulation apparatus includes a pipeline simulation unit is operable to simulate a group of instructions comprising a plurality of instructions to be executed simultaneously. The instruction simulation unit is operable to simulate a sequential execution, of the group of instructions on an instruction-by-instruction basis, based on the simulation result performed by the pipeline simulation unit. The instruction simulation unit generates the simulation result by undoing the simulation where an instruction included in the group of instructions that has just been simulated by the pipeline simulation unit.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: November 27, 2007
    Assignee: Matsushita Electric, Industrial Co., Ltd.
    Inventor: Kohsaku Shibata
  • Patent number: 7286976
    Abstract: Methods and apparatuses for emulating a circuit design that includes an in-circuit memory. Sets of reconfigurable logic resources are configured to emulate a logic element of a circuit, where the circuit may include a plurality of logic elements. A memory resource is configured to emulate a portion of the in-circuit memory. Reconfigurable interconnect resources are configured to interconnect the sets of configurable logic resources to the memory resource by way of a memory access arbiter. The memory access arbiter is configured to arbitrate and serialize accesses for the memory resource by the sets of reconfigurable logic resources in an emulation cycle, in accordance with associated priority levels. The priority level of the set of reconfigurable logic resources may be dependent on timing requirements of the set of reconfigurable logic resources and on timing characteristics of the associated logic element of the circuit.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: October 23, 2007
    Assignee: Mentor Graphics (Holding) Ltd.
    Inventors: Philippe Diehl, Gilles Laurent, Frederic Reblewski
  • Patent number: 7280947
    Abstract: Featured are a system and method for designing a gear driving system. The designing system includes a characteristic setting section, calculating section and comparing section. The calculating section simulates an oscillation that is caused in the final gear of the gear driving system, based on the gear characteristic value(s) set in the characteristic setting section. The comparing section judges whether or not the frequency mid amplitude of the oscillation obtained by the simulation fall within an acceptable range. If the frequency and amplitude do not fall within the acceptable range, the characteristic changing section changes the setting of a gear characteristic value, and the processes of the calculating section and the comparing section, as well as that of the characteristic changing section are repeated until it is judged that one of the frequency or amplitude of the simulated oscillation falls within the acceptable range.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: October 9, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kiwamu Morita, Yoshinobu Okumura, Tomohiko Okada
  • Patent number: 7272544
    Abstract: Integrated modeling and symbolic manipulation is leveraged for the derivation, construction, maintenance, and reuse of application-independent models. Related models created for different applications share a common ancestry and maintain model consistency while enabling the models to share information about the process. Environment independent proper ancestor models (PAMs) are created for generic components of a process, such as a distillation or flash column. Models underlying an application may be comprised of various representations of multiple such processes corresponding to many different physical components. PAMs contain symbolic representations of different sub processes that occur within a process or component. A user makes assumptions about the component, by indicating how sub processes are to be considered or not considered. PAMs are then modified in accordance with the assumptions to derive a specific environment model (SEM).
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: September 18, 2007
    Assignee: Honeywell International Inc.
    Inventors: Vipin Gopal, Jan Jelinek, Alan Haggerty