Abstract: An adjuster can provide a potentiometric type of adjustment with a control generator, a driver and a transducer. The control generator can provide an adjusting signal to the driver. The driver is coupled to the control generator for providing a drive signal in response to the adjusting signal. The transducer has its input coupled to the driver and this input is electrically isolated from its output. This output of the transducer can conduct by a variable amount in response to the adjusting signal, to simulate potentiometric action.

Abstract: A cash counting machine including a bill feed mechanism that transfers bills individually from an input hopper to an output tray including a microprocessor control system. The machine operates in two modes, including a batch mode in which it transfers a selected number of bills, as selected by an operator, to the output tray, and a count mode in which it transfers all of the bills to the output tray and keeps a running count of the number of bills, as well as the total value of money if the operator has entered a denomination value. The microprocessor also determines whether the bills are of the proper size. In an alternate embodiment, for use with currencies in which the different denominations have different sizes, the microprocessor determines the size of the bills and their respective denominations.

Abstract: A system for sensing the position of an object such as a rotating member has a plurality of photocouplers coupled with the interposition of a rotary disc having slits and rotating with the object. The system further has a position signal generating circuit for receiving signals produced by the photocouplers and producing a series of component position signals differing in phase successively by a predetermined phase difference, a counting circuit having an up/down count for determining the position of the object by counting occurrences of a predetermined change recurring periodically in the component position signals, and a direction determining circuit for producing an up/down signal for controlling the counting mode of the up/down counter. Each time the predetermined change occurs in any one of the component position signal, the direction determining circuit determines the order in which the change occurs in two successive component position signals.

Abstract: A duty control circuit for controlling a duty factor in various industrial applications is proposed. It comprises a n-pulse counter, a m-pulse counter, another n-pulse counter, and a magnitude comparator. The magnitude comparator compares the count of the first counter with the count of the third counter and the duty control circuit gives a signal corresponding to ON when the former is larger than or equal to the latter and a signal corresponding to OFF when the former is smaller than the latter.

Abstract: In an arrangement comprising a phase control circuit the phase comparator, when receiving input pulses with which the clock pulses are in phase, will produce an output signal having a pulse frequency which is twice the pulse frequency of the input pulses. The ripple on the control-voltage for the oscillator to be controlled resulting therefrom is compensated for by adding to the output signal of the phase detector a signal which is opposite in phase to the output signal. The result is that only frequency- and phase errors produce a ripple (change) on the output signal.

Abstract: A surface wave microwave antenna is presented in which transmission or reception of microwave energy is effected by discontinuities in a dielectric body positioned between a central feeder element and a ground plane. When used as a transmitter, the central disc propagates surface waves in the dielectric body in expanding circles; and the discontinuities in the dielectric body act as radiating or scattering sites to couple the waves to free space. When used as a receiver, the reverse will occur.

Abstract: The invention relates to a process for using a binary register with n bistable cells making it possible to determine the ratio of two frequencies and an apparatus for performing the process. This use process consists of supplying to a counting input of the binary register with n bistable cells a first pulse signal S.sub.1 of frequency F.sub.1 and to a shift input of said register a second pulse signal S.sub.2 of frequency F.sub.2 with F.sub.1 >>F.sub.2, the register content being incremented at each pulse of the first signal S.sub.1 and divided by two at each pulse of the second signal S.sub.2, whereby the register content can also be loaded into a buffer register at each pulse of the second signal S.sub.2. The invention more particularly applies frequency discrimination, the determination of an unknown frequency on the basis of a known frequency and to the control of analog display means of the logarithm to base two of the ratio of two frequencies.

Abstract: A waveform converter circuit for producing an output square waveform, having a unity mark/space ratio, from an input sinusoidal waveform which can have a large peak-to-peak amplitude range and a large d.c. voltage level range. The circuit comprises a differential amplifier which receives the input waveform at the inverting input. The output of the amplifier is applied to a D-type flip-flop. The flip-flop Q-output is fed via a switched-capacitor filter to the inverting input to provide a corrected d.c. voltage level for the input waveform at this input. The flip-flop Q-output is fed via a switched-capacitor filter to the non-inverting input to provide a slicing level at this input. When the output square waveform has a 1 to 1 mark/space ratio, the corrected d.c. voltage level equals the slicing level. Thus, the circuit will respond to an input waveform with a small peak-to-peak amplitude in the presence of an initial large d.c. voltage level of the input waveform.

Abstract: A CCD output signal generating circuit includes a CCD type charge transfer device for transferring and outputting signal charges in response to the drive signal of a frequency f.sub.c, an output circuit for generating an output signal corresponding to the output signal charges from the CCD type charge transfer device, and a correlated double sampling circuit. The CDD output signal generating circuit also has a low-pass filter circuit which, having a cut-off frequency set within a range of 2.5f.sub.c to 4f.sub.c, and being connected between the output circuit and the correlated double sampling circuit, acts to filter an output signal from the output circuit before supplying the signal to the correlated double sampling circuit.

Abstract: A shift register having a simple circuit structure and used, for example, in a dynamic RAM device for a refresh operation. The shift register includes a plurality of circuit stages mutually connected in cascade. Each of the circuit stages includes a first transistor, for a transfer gate, which is turned on and off by a first clock signal and to which is input the output signal of the previous circuit stage. A second transistor is provided whose gate electrode is connected to the output of the first transistor, whose drain or source electrode receives a second clock signal having a different phase from the first clock signal, and whose source or drain electrode outputs an output signal. Each circuit stage also includes a reset circuit for rendering the input portion of the first transistor to a reset condition on the basis of the output signal, thereby sequentially transmitting data through each circuit stage.

Abstract: In a CCD, especially in an image sensor device, the information density can be doubled by sequentially switching the electrodes between a clock signal and a reference signal. Clock signals and reference signals are obtained as output signals of a shift register controlled by a monophase or multiphase clock. The register is provided, for example, using C-MOS technology. Information at the input terminal of the first stage of the shift register in combination with clock pulse signals at the register clock, determine the output signals of the next stage of the shift register. Hence, these input signals determine the voltage variations at the electrodes connected to the outputs of the register stages.

Abstract: Sensors in the infeed and output stackers, under control of the microprocessor, monitor the sheets. The apparatus is started automatically by placing sheets in the infeed. A count of the sheets is developed and displayed as the sheets are fed. When the infeed is empty and the output contains sheets, the count is retained. If sheets are removed from the outfeed, the count is retained and is reset only after more sheets are placed in the input. The same rules obtain for batching. The sensors cooperate with singles, holes and doubles detectors and have their gain adjusted depending upon sheet density. Automatic threshold adjustment circuits compensate for dust build-up and component aging. Upon sheet detection, the sensing circuit threshold level is instantaneously shifted to prevent an abrupt change in intensity from the sheet covering the sensor to provide an erroneous indication of the presence of a subsequent sheet or sheets.

Abstract: Method and apparatus for monitoring the time rate of successive events the rate of occurrence of which can vary over a wide range by: detecting the successive events during a succession of consecutive time intervals of equal duration; producing successive counts each representing the number of events occurring during each interval in which at least one event occurs; producing successive counts each representing the number of intervals between the end of a respective interval in which at least one event occurred and the end of the immediately preceding interval in which at least one event occurred; and storing representations of the successive counts produced.

Abstract: A counter for counting clock pulses and having a plurality of output bits successively numbered from a first output bit to a highest output bit. The counter includes a plurality of bistable devices, one bistable device being associated with each output bit, and each bistable device including a clock input for receiving clock pulses to be counted, and an output for providing one of the output bits and its complement. The bistable device which is associated with the first output bit toggles with the receipt of each clock pulse to be counted. The counter also includes a decode section responsive to the outputs of the plurality of bistable devices for providing decoded signals, and a select section for receiving the clock pulses to be counted and responsive to the decoded signals and the complement of the first output bit. The select section selects which of the plurality of bistable devices associated with the second and higher output bits will toggle on the receipt of the next clock pulse.

Abstract: A counting circuit includes a digital counter for counting the pulses of an input signal during a counting interval and a pair of digital latches for latching the binary state of the input signal at the beginning and end of the counting interval, respectively. The latched binary states of the input signal and the pulse count of the digital counter are evaluated by an interpreter such as logic circuitry or a microprocessor. The interpreter resolves the pulse count into half clock cycles by comparing the binary states and in response adjusts the pulse count by the addition or subtraction of half a clock cycle.

Abstract: A square wave with a 50% duty cycle which has frequency twice that of an input square wave also having a 50% duty cycle is obtained by generating from the incoming square wave two waveforms having 75% duty cycles with the two waveforms 180.degree. out of phase with each other. The two waveforms are combined in an ANDing operation to obtain an output waveform which is a square wave with twice the frequency of the incoming square wave. In similar fashion, using additional similar circuits and gating, tripling is possible.

Abstract: A bidirectional barrel shift circuit includes an input switching circuit having a plurality of parallel input lines and the corresponding number of first and second signal line pairs associated to the respective input lines. This input switching circuit is operative to selectively connect each of the input lines to one line of the associated first and second signal line pair. There is also provided an output switching circuit connected to all the first and second singal lines and having output lines of the number corresponding to that of the input lines. This output switching circuit is operative to connect either the first signal lines or the second signal lines to the corresponding output lines. A barrel shift matrix is connected to the first and second signal lines and is controlled by a shift number controller so as to produce between the first and second signal lines a connection pattern sufficient for realizing a given shift number.

Abstract: The electronic clinical thermometer in accordance with the present invention comprises a thermometric oscillator for converting a variation in the temperature sensitive resistance to a frequency corresponding to the temperature, a thermometric counter for counting the oscillation frequency of the thermometric oscillator to convert the frequency to a temperature value, a maximum value memory circuit for detecting the maximum value by comparing in succession the content of the thermometric counter, a display circuit for digitally displaying the content of the maximum value memory circuit, and a controlling circuit for controlling the thermometric oscillator so as to discontinue the oscillation of the thermometric oscillator at a prescribed time after the beginning of temperature detection or detection of a maximum value.

Abstract: Apparatus for repeatedly generating a staircase ramp voltage pulse on a bus connected to a capacitive load employing a set of DC voltage sources, each producing a voltage of a step in the staircase ramp voltage. A storage capacitor is connected between the output terminal of each voltage source and ground. An FET switch is connected between each of the output terminals and the bus and between ground and the bus. A timing circuit closes each of the FET switches in order to produce a staircase ramp voltage on the bus charging the capacitive load. When it is desired to discharge the capacitive load, the timing circuit then closes the switches in reverse order. Each storage capacitor is charged by the discharging capacitive load to a voltage above the voltage of its associated voltage source. The energy thus stored is used during the next cycle to contribute to the energy required to charge the capacitive load on the bus.

Abstract: A system for and a method of generating a four phase clock signal is disclosed. The system includes an oscillator circuit that generates a clocking signal of frequency F. A flip-flop, under control of a Master Clear signal, establishes the first stage of a shift register in an active state while the clocking signal drives the shaft register to serial, end-around, shift the active state through the shift register. The parallel outputs of the shift register are coupled to respectively associated pulse generators which are also triggered by the clock signal to emit the four phase clock signal therefrom. The method ensures that the first phase signal is always the first signal to be emitted from the system while compatible semiconductor circuitry is used throughout and is operated at or near the frequency limit of the semiconductor circuitry used.