Abstract: The present invention relates to a digital indication type measuring apparatus comprising a main body of the measuring instrument such as slide calipers, incorporating therein a data processing circuit for digitally indicating measured data and a printer detachably connected to the main body of the measuring instrument. The connection between the main body of the measuring instrument and the printer is effected by a jack provided on the main body of the measuring instrument and a connector provided at the forward end of a cord extending from the printer. A switch for outputting the measured data to the printer is provided on the connector, whereby it becomes possible to use the main body of the measuring instrument such as the slide calipers as a single component or to print the measured data as necessary, so that the functional effect of the measuring instrument can be expanded.

Abstract: A device for detecting a momentary cutoff of an AC power source which is used with a data processing apparatus or the like. The device determines that a momentary cutoff has occurred in the AC power source when an actual rotation speed of a motor energized by the AC power source for rotation is lower than a predetermined rotation speed.

Abstract: A binary ripple counter having exclusive OR coupling elements between the counter bistables for use in a digital delay by events circuit of a display device such as an oscilloscope. The counter is programmable.

Abstract: A binary up/down counter stage particularly suitable for CMOS implementation. The counter stage includes an exclusive OR gate having a first input for receiving a toggle signal, a flip-flop having a data input coupled to the output of the exclusive OR gate and Q and Q outputs, the Q output of which provides the stage output and a feedback to the second input of the exclusive OR gate, and a multiplexer having first and second inputs coupled to the Q and Q of the flip-flop respectively, the output of the multiplexer being logically ANDED with a toggle-in signal to provide a toggle-out signal for a further counter stage in cascade.

Abstract: Sensors in the infeed and output stackers, under control of the microprocessor, monitor the sheets. The apparatus is started automatically by placing sheets in the infeed. A count of the sheets is developed and displayed as the sheets are fed. When the infeed is empty and the output contains sheets, the count is retained. If sheets are removed from the outfeed, the count is retained and is reset only after more sheets are placed in the input. The same rules obtain for batching. The sensors cooperate with singles, holes and doubles detectors and have their gain adjusted depending upon sheet density. Automatic threshold adjustment circuits compensate for dust build-up and component aging. Upon sheet detection, the sensing circuit threshold level is instantaneously shifted to prevent an abrupt change in intensity from the sheet covering the sensor to provide an erroneous indication of the presence of a subsequent sheet or sheets.

Abstract: A high-speed programmable timing generator in which a continuously cycling binary count is compared with an input data word. Predetermined bits, starting from the highest-order end of the counter, can be selectively inhibited to effectively vary the cycle period of the counter. The digital word with which the output of the counter is compared can be varied to set the reference phase of the output timing pulse stream. Further, fine delay adjustment of the phase of the output timing pulse stream is effected by a controllable phase-locked loop.

Abstract: The disclosed apparatus automatically retrieves desired information on an information bearing medium having information and marks. In the retrieving apparatus, the marks are detected and counted during the feed of the information bearing medium. In accordance with the number of the counted marks, the feeding of the data bearing medium is controlled to retrieve the desired data. The apparatus is provided with at least three mark-detecting means for successively detecting the mark and memory means for memorizing the detections of the mark by the respective mark-detecting means, and a mark counting signal is formed from the content in said memory means and the counting signal is counted in order to eliminate the possibility that one and same mark may erroneously be counted twice or more when the feeding speed of the information bearing medium is abruptly changed.

Abstract: A variable frequency divider which includes a feedback shift register having a feedback gate of NOR type, a delay shift register for delaying output data from the feedback shift register by one clock, a control shift register having a control gate of AND type, a feedback circuit for feeding output data from the delay shift register and from the control shift register back to the feedback gate, and an expander which receives output data from the feedback shift register and produces a control signal according to said frequency dividing input and a frequency division ratio instruction signal. The control gate receives output data from the delay shift register and the control signal.

Abstract: Current source circuitry consisting of a first n-channel field effect transistor (FET) and voltage generator circuitry coupled to the gate of the first FET. The voltage generator circuitry acts to control the current through the first FET such that it is essentially constant even with power supply, temperature, and many processing variations. The voltage generator circuitry consists of a second FET, a two input differential operational amplifier, a resistor, and an n-p-n transistor if the resistor has a positive temperature coefficient. A negative feedback path using the amplifier and the second FET ensures against current changes in the first and second FETs even if there are changes in one of the power supply levels and/or many semiconductor processing variations.

Abstract: A phase/frequency detector to detect the phase/frequency difference between two signals comprises a first bistable circuit to produce a first output pulse in response to one of the two signals; a second bistable circuit to produce a second output pulse in response to the other of the two signals; a gate circuit coupled to the first and second bistable circuits responsive to the first and second output pulses to produce a reset pulse to reset the first and second bistable circuits after a predetermined time delay. A first circuit arrangement is coupled to the first bistable circuit and the gate circuit to reduce the width of the first output pulse and a second circuit arrangement is coupled to the second bistable circuit and the gate circuit to reduce the width of and invert the second output pulse. The second circuit arrangement includes a third circuit arrangement to equalize turn on and turn off times of the reduced width first output pulse and the reduced width second output pulse.

Abstract: A binary counter consists of a plurality of unit stages each having a bistable circuit, a buffer circuit for generating an output corresponding to an output state of the bistable circuit, a switching circuit for supplying an output of the buffer circuit to the bistable circuit, and a coincidence gate for supplying a clock signal to the next unit stage in accordance with the predetermined output state of the bistable circuit.

Abstract: A blood counter comprising a sheathed flow cell; a light source including what has the wavelengths causing absorption of light by hemoglobin in the blood; means for receiving transmitted light; means for receiving the scattered light; a decision assembly for judging, based on the output signals detected by means for receiving the transmitted light and scattered light, (i) the flowing cells therein to be a red blood cell if the degree of absorption is larger than the preselected level and (ii) the other to be a blood platelet if the intensity of the scattered light is larger than a certain level and if the degree of absorption is smaller than said preselected level; and a counter assembly for counting out the red blood cells and blood platelets.

Abstract: A logic circuit is formed on a gate array chip together with a custom-circuit. Bonding pads mounted on the gate array chip are used as the terminals which send forth or receive data and control signals. The logic circuit is provided with a shift register for holding data to test the flip-flops of the custom-circuit and output data from the flip-flops. The shift register comprises the stages each of which holds 1-bit data selected by a read control signal. The output terminals of the stages are respectively connected to the input terminals of the flip-flops of the custom-circuit through the AND gates which are rendered conducting in response to a set control signal. The output terminals of the flip-flops are connected to the input terminals of the respective stages of the shift register.

Abstract: A compact, unitary non-contacting counting device includes a housing with contains a photoelectric sensor adapted to monitor the passage of articles and emit responsive electrical signals and a totalizer for receiving such electrical signals or a related binary output change of state indication and maintaining a count. The housing is unitary and is sealed to resist undesired entry of foreign matter. The housing is preferably generally L-shaped having a first leg containing the photoelectric sensor which is adapted to emit and receive light in a first direction and a second leg which contains the totalizer which is adapted to display the count in the direction which may be opposed to or perpendicular to the second direction. Separate power supplies may be employed for the photoelectric sensor and the totalizer. Lenses or fiber optics may be employed to improve the efficiency of transmission of light from the source to the object or target and return of the light from the object or target.

Abstract: A circuit approach is illustrated for simplifying a count divider circuit by applying selected outputs of the counter to a J-K flip-flop as input to the J-K terminals whereby a comparatively high speed response is returned for presetting the counter as compared to the prior art approach which either required much more circuitry or intolerable time delays.

Abstract: A charge transfer device has one or more charge injection areas each having an input diffusion layer and two or more input gate electrodes. An input signal is applied to the input diffusion layer, a clock voltage is applied to one of the input gates and an input reference voltage is applied to the other input gate to inject a signal charge proportional to a difference between the input reference voltage and the input signal, and the signal charge is sequentially transferred. A magnitude of the input reference voltage is changed in accordance with a magnitude of a maximum value of the input signal so that transfer of charges which do not contribute to signal component is suppressed and a transfer efficiency is improved.

Abstract: A passive duplexer for electromagnetic waves operated within the millimetric wave range. The duplexer comprises a first horn associated with a radar transmitter and having a propagation axis (.DELTA..sub.1), a plane circular grid inclined at 45.degree. with respect to (.DELTA..sub.1), and a second horn associated with the radar receiver and having an axis (.DELTA..sub.2) at right angles to (.DELTA..sub.1). The grid is formed by a network of resonant slots equipped with at least one diode.

Abstract: D.C. reconstruction of sampled CCD output signals is achieved by subtracting the output current pulses of two CCDs (or subtracting parallel outputs of the same CCD) with a differencing circuit containing two biasing current mirrors, a current sink device and an output capacitor. The two current mirrors are used with each biasing the output of a complementary CCD to positive and acting to mirror the CCD output current. A third current mirror converts the output of one of the CCDs into a current sink. An output capacitor performs subtracting by converting all outputs to voltage and combining the positive biased output of one CCD with the current said output of the second CCD.

Abstract: A fractional divider which functions as a prescaler in a phase lock loop-based frequency synthesizer provides a selectable prescaling factor to the divide-by-N programmable divider. The prescaling factor can assume either the value 2 or 2+1/N. The fractional division, occurring in front of the programmable divider, permits a periodic signal to be generated by that device, while recapturing the frequencies lost to prescaling. When operating in the divide-by-(2+1/N) mode, the fractional divider drops one input clock pulse each time the output signal of the programmable divider assumes a predetermined binary state.

Abstract: An electronic postage meter includes electronic circuitry for providing an accounting of the number of mailpieces imprinted with postage, and the amount of postage imprinted on such mailpieces. An electro-optic sensor connects with a mechanical drive of a printing drum of the meter to sense successive rotations of the printing drum, one rotation occurring for each imprinting of postage. A comparison circuit compares the one-bit signal provided by the electro-optic sensor with the least significant bit of a count of the mailpieces, which count is provided electronically by the accounting function. Any discrepancy between the least significant bit of the mechanical count and the least significant bit of the electronic count serves as a warning of a malfunction, or of tampering, of the postage unit. An error-signal circuit connected to the comparison circuit terminates operation of the meter upon the occurrence of a discrepancy between the mechanical and electrical counts.