Patents Examined by Kathleen Duda
  • Patent number: 11520232
    Abstract: Provided is a film for application to a 3D sample, the film including a photoresist layer that has alignment or direction marks thereon. After the fine pattern of the photoresist layer or coat is exposed, the photoresist layer is applied to a desired position of the 3D sample by aligning the alignment or direction marks of the film with alignment or direction marks on the 3D sample. This allows for transfer of an appropriate fine pattern. Part or all of the thickness or area of the photoresist layer is developed to form projections or depressions in the photoresist layer before the film is applied to the 3D sample.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: December 6, 2022
    Assignee: Toyota School Foundation
    Inventor: Minoru Sasaki
  • Patent number: 11480874
    Abstract: A rinse process is described for processing an initially patterned structure formed with an organometallic radiation sensitive material, in which the rinse process can remove portions of the composition remaining after pattern development to make the patterned structure more uniform such that a greater fraction of patterned structures can meet specifications. The radiation sensitive material can comprise alkyl tin oxide hydroxide compositions. The rinsing process can be effectively used to improve patterning of fine structures using extreme ultraviolet light.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: October 25, 2022
    Assignee: Inpria Corporation
    Inventors: Michael Kocsis, Peter De Schepper, Michael Greer, Shu-Hao Chang
  • Patent number: 11437238
    Abstract: Methods and film stacks for extreme ultraviolet (EUV) lithography are described. The film stack comprises a substrate with a hard mask, bottom layer, middle layer and photoresist. Etching of the photoresist is highly selective to the middle layer and a modification of the middle layer allows for a highly selective etch relative to the bottom layer.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: September 6, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Nancy Fung, Chi-I Lang, Ho-yung David Hwang
  • Patent number: 11429027
    Abstract: An extreme ultraviolet lithography (EUVL) method includes providing at least two phase-shifting mask areas having a same pattern. A resist layer is formed over a substrate. An optimum exposure dose of the resist layer is determined, and a latent image is formed on a same area of the resist layer by a multiple exposure process. The multiple exposure process includes a plurality of exposure processes and each of the plurality of exposure processes uses a different phase-shifting mask area from the at least two phase-shifting mask areas having a same pattern.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shinn-Sheng Yu, Ru-Gun Liu, Hsu-Ting Huang, Chin-Hsiang Lin
  • Patent number: 11366386
    Abstract: A patterning process, including: forming the first resist film from first resist material containing an acid generator and thermosetting compound having a hydroxy group and/or carboxy group protected by an acid-labile group; forming the second resist film on first resist film from a second resist material containing a metal compound (A) and a sensitizer; irradiating the first and second resist film with a high energy beam or an electron beam to perform pattern exposure to deprotect the hydroxy group and/or carboxy group in a pattern exposed portion of first resist film and to form a crosslinked portion of the component (A) with the deprotected hydroxy and/or carboxy group on the pattern exposed portion; and developing the second resist film with a developer to give a metal film pattern composed of the crosslinked portion. This provides a method for forming a thin film resist pattern with higher resolution and higher sensitivity.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 21, 2022
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Tsukasa Watanabe, Tsutomu Ogihara
  • Patent number: 11361878
    Abstract: The present invention relates to a method for manufacturing an insulating layer which can minimize the degree of warpage caused by polymer shrinkage at the time of curing and secure the stability of a semiconductor chip located therein, and a method for manufacturing a semiconductor package using an insulating layer obtained from the manufacturing method of the insulating layer.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: June 14, 2022
    Assignee: LG CHEM, LTD.
    Inventors: Woo Jae Jeong, You Jin Kyung, Byung Ju Choi, Bo Yun Choi, Kwang Joo Lee, Min Su Jeong
  • Patent number: 11360388
    Abstract: Techniques herein include processes and systems by which a reproducible CD variation pattern can be mitigated or corrected to yield desirable CDs from microfabrication patterning processes, via resolution enhancement. A repeatable portion of CD variation across a set of wafers is identified, and then a correction exposure pattern is generated. A direct-write projection system exposes this correction pattern on a substrate as a component exposure, augmentation exposure, or partial exposure. A conventional mask-based photolithographic system executes a primary patterning exposure as a second or main component exposure. The two component exposures when combined enhance resolution of the patterning exposure to improve CDs on the substrate being processed without measure each wafer.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: June 14, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Anton deVilliers, Ronald Nasman, Jeffrey Smith
  • Patent number: 11327396
    Abstract: A mask blank for manufacturing a transfer mask. A thin film (2) includes a material containing a metal, silicon, and nitrogen; a ratio of metal content[atom %] to the total content [atom %] of metal and silicon in the thin film (2) is 15% or less. When the thin film is subjected to an analysis of a secondary ion mass spectrometry and a distribution of a secondary ion intensity of silicon in depth direction, a ratio of 1.6 or less is obtained of (i) a maximum peak [Counts/sec] of a secondary ion intensity of silicon at a surface layer region, which is opposite from a transparent substrate (1), of the thin film (2), divided by (ii) an average value [Counts/sec] of a secondary ion intensity of silicon in a depth direction of an inner region, which is a region excluding the surface layer region and a vicinity region with an interface, of the transparent substrate (1) of the thin film (2).
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: May 10, 2022
    Assignee: HOYA CORPORATION
    Inventors: Atsushi Kominato, Toshiyuki Suzuki
  • Patent number: 11320738
    Abstract: In a pattern formation method, a bottom layer is formed over an underlying layer. A middle layer is formed over the bottom layer. A resist pattern is formed over the middle layer. The middle layer is patterned by using the resist pattern as an etching mask. The bottom layer is patterned by using the patterned middle layer. The underlying layer is patterned. The middle layer contains silicon in an amount of 50 wt % or more and an organic material. In one or more of the foregoing and following embodiments, an annealing operation is further performed after the middle layer is formed.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: May 3, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Wei Wang, Ching-Yu Chang, Shang-Wern Chang, Yen-Hao Chen
  • Patent number: 11300881
    Abstract: A photolithography patterning stack and method for repairing defects in the stack. The stack includes an organic planarization layer, a hardmask layer, and a plurality of patterned photoresist lines in contact with the hardmask layer. A plurality of trenches is situated between the plurality of patterned photoresist lines. Each trench exposes a portion of the hardmask layer. A repairing layer is formed in contact with and only bonded to surfaces of the plurality of patterned photoresist lines. The method includes forming a photolithographic patterning stack. The stack includes at least a hardmask layer formed on one or more underlayers and a photoresist layer formed in contact with the hardmask layer. The photoresist layer is patterned into a plurality of patterned portions. A repairing layer is formed in contact with and only bonded to surfaces of each patterned portion of the plurality of portions.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: April 12, 2022
    Assignee: International Business Machines Corporation
    Inventors: Luciana Meli Thompson, Jing Guo, Nelson Felix, Ekmini Anuja De Silva
  • Patent number: 11294286
    Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Gun Liu, Chin-Hsiang Lin, Cheng-I Huang, Chih-Ming Lai, Chien-Wen Lai, Ken-Hsien Hsieh, Shih-Ming Chang, Yuan-Te Hou
  • Patent number: 11294285
    Abstract: A method for manufacturing the circuit board comprises following steps of forming a silver layer on each of two opposite surfaces of an insulating substrate, and forming a copper layer on each silver layer, thereby obtaining a middle structure; defining at least one through-hole on the middle structure, and each through-hole extending through each copper layer; forming a copper wiring layer on the copper layers to cover each through-hole and a portion region of the copper layers, the copper wiring layer comprising a copper conductive structure passing through each through-hole, the copper conductive structure connecting the copper layers; removing the copper layers not covered by the copper wiring layer; and etching the silver layers to form a silver wiring layer corresponding to the copper wiring layer, wherein a first etching liquid, which does not etch the copper wiring layer, is used for etching the silver layers.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: April 5, 2022
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: Xian-Qin Hu, Mei Yang, Jun Dai
  • Patent number: 11281107
    Abstract: Methods for performing a lithography process are provided. The method for performing a lithography process includes forming a resist layer over a substrate and exposing a portion of the resist layer to form an exposed portion between unexposed portions. The method for performing a lithography process further includes developing the resist layer to remove the exposed portion of the resist layer such that an opening is formed between the unexposed portions and forming a post treatment coating material in the opening and over the unexposed portions of the resist layer. The method for performing a lithography process further includes reacting a portion of the unexposed portions of the resist layer with the post treatment coating material by performing a post treatment process and removing the post treatment coating material.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hui Weng, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 11249398
    Abstract: A method for producing a plated shaped structure, includes applying a photosensitive resin composition on a substrate to form a photosensitive resin coating film. The photosensitive resin composition includes: (A) a resin whose solubility in alkali is capable of being increased by an action of an acid; (B) a photoacid generator; and (C) a compound which is capable of being decomposed by an action of an acid to form a primary or secondary amine. The photosensitive resin coating film is exposed to light. The photosensitive resin coating film is developed after the exposing to light to form a resist pattern. A plating process is performed using the resist pattern as a mask.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: February 15, 2022
    Assignee: JSR CORPORATION
    Inventors: Hirokazu Sakakibara, Hirokazu Itou, Tomoyuki Matsumoto, Kazuto Watanabe
  • Patent number: 11249399
    Abstract: A photolithography method, a method of preparing a flexible substrate and a photoresist drying device are provided. The photolithography method includes: providing a base substrate on which a material layer to be etched is formed, in which the base substrate includes an intermediate region and a peripheral region surrounding the intermediate region; coating a layer of photoresist on the base substrate, in which the photoresist is coated in the intermediate region and the peripheral region, and is formed to cover the material layer to be etched; and drying the photoresist and simultaneously performing a first exposure process on the photoresist coated in the peripheral region.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: February 15, 2022
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Cheng Tang, Zebin Sun, Zhen Zhen, Hao Zhang, Shitao Zhang, Xinxing Fan, Xudong Zhang
  • Patent number: 11243469
    Abstract: A substrate processing apparatus includes a development processor and a reversal film former, and processes a substrate having one surface on which a resist film made of a photosensitive material is formed. The development processor forms a resist pattern on the one surface of the substrate by performing development processing on a resist film using a development liquid. A reversal film former forms a reversal film having etch resistance higher than that of the resist film on the one surface of the substrate to cover the resist pattern while regulating a temperature of the substrate in a certain range after the development processing is performed by the development processor.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: February 8, 2022
    Inventors: Masahiko Harumoto, Koji Kaneyama, Yuji Tanaka, Masaya Asai
  • Patent number: 11231649
    Abstract: A patterning process, including steps of: forming the first resist film from the first resist material containing a thermosetting compound having a hydroxy group and/or a carboxy group each protected by an acid-labile group, an acid generator, and a sensitizer; irradiating the first resist film with a high energy beam or an electron beam to perform pattern exposure to deprotect the hydroxy group and/or carboxy group in a pattern exposed portion; forming the second resist film from second resist material containing (A) metal compound on the first resist film, and forming a crosslinked portion wherein the component (A) and deprotected hydroxy group and/or deprotected carboxy group are crosslinked on the pattern exposed portion; and developing the second resist film with a developer to give a metal film pattern composed of the crosslinked portion. This provides a method for forming a thin film resist pattern with higher resolution and higher sensitivity.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: January 25, 2022
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Tsukasa Watanabe, Tsutomu Ogihara
  • Patent number: 11226562
    Abstract: A method of manufacturing a semiconductor structure includes providing a mask including a first substrate; a first mask layer disposed over the first substrate, including a plurality of first recesses extended through the first mask layer; a second mask layer disposed over the first mask layer and including a plurality of second recesses extended through the second mask layer; providing a second substrate including a photoresist disposed over the second substrate; and projecting a predetermined electromagnetic radiation through the mask towards the photoresist, wherein the first mask layer is at least partially transparent to the predetermined electromagnetic radiation, the second mask layer is opaque to the predetermined electromagnetic radiation, and at least a portion of the second mask layer is disposed between two of the plurality of second recesses.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yung-Yao Lee, Yi-Ping Hsieh
  • Patent number: 11215927
    Abstract: Provided is a substrate treating composition. The substrate treating composition includes a first monomer, a second monomer and an acid. The first monomer is represented by Formula 1 and the second monomer is represented by Formula 7. The molecular weight of the solid content of the substrate treating composition including the first monomer, the second monomer and the acid is from about 1,000 g/mol to about 50,000 g/mol.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: January 4, 2022
    Assignees: SAMSUNG ELECTRONICS CO., LTD., NISSAN CHEMICAL CORPORATION
    Inventors: Ju-Young Kim, Hyunwoo Kim, Makoto Nakajima, Satoshi Takeda, Shuhei Shigaki, Wataru Shibayama
  • Patent number: 11209728
    Abstract: Present disclosure provide a method for fabricating a mask, including obtaining a target pattern to be imaged onto a substrate, providing a first scattering bar and a second scattering bar adjacent to consecutive edges of the target pattern, identifying a first length of the first scattering bar and a second length of the second scattering bar, connecting the first scattering bar and the second scattering bar when any of the first length and the second length is smaller than a predetermined value, identifying a separation between the first scattering bar and the second scattering bar subsequent to identifying the first length and the second length, disposing the first scattering bar and the second scattering bar in a first fashion when the separation is equal to zero, and disposing the first scattering bar and the second scattering bar in a second fashion when the separation is greater than zero.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Huang-Ming Wu, Jiun-Hao Lin, Jia-Guei Jou, Chi-Ta Lu, Chi-Ming Tsai