Patents Examined by Kathleen Duda
  • Patent number: 11209736
    Abstract: A method for manufacturing a photomask is provided. The method includes: receiving a substrate having a hard mask disposed thereover; forming a patterned photoresist over the hard mask; patterning the hard mask using the patterned photoresist as a mask; and removing the patterned photoresist. The removing of the patterned photoresist includes: oxidizing organic materials over the substrate; applying an alkaline solution onto the patterned photoresist; and removing the patterned photoresist by mechanical impact. A method for cleaning a substrate and a photomask are also provided.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hsin Hsu, Hao-Ming Chang, Shao-Chi Wei, Sheng-Chang Hsu, Cheng-Ming Lin
  • Patent number: 11199778
    Abstract: A method of making an adhesion layer of an extreme ultraviolet (EUV) stack is presented. The method includes grafting an ultraviolet (UV) sensitive polymer brush on a hardmask, the polymer brush including a UV cleavable unit, depositing EUV resist over the polymer brush, exposing the EUV resist to remove the EUV resist in exposed areas by applying a developer, and flooding the exposed area with a UV light and a solvent developer to remove exposed portions of the polymer brush.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: December 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jing Guo, Bharat Kumar, Ekmini A. De Silva, Jennifer Church, Dario Goldfarb, Nelson Felix
  • Patent number: 11187984
    Abstract: A resist patterning method includes a resist layer forming step, a patterned exposure step, a flood exposure step, and a developing step. In the resist layer forming step, a resist layer is formed on a substrate. In the patterned exposure step, a sensitizer is produced from a sensitizer precursor in the resist layer. In the flood exposure step, flood exposure is performed on the resist layer in which the sensitizer has been produced to produce an acid from a strong acid generator. In the developing step, the resist layer is developed. The patterned exposure step includes: producing a strong acid from the strong acid generator; producing the sensitizer through a reaction between the strong acid and the sensitizer precursor; producing a weak acid through a reaction between the strong acid and a base; and producing the sensitizer through a reaction between the weak acid and the sensitizer precursor.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: November 30, 2021
    Assignee: OSAKA UNIVERSITY
    Inventor: Seiichi Tagawa
  • Patent number: 11175582
    Abstract: This disclosure relates to a photosensitive stacked structure that includes first and second layers, in which the first layer is a photosensitive, dielectric layer and the second layer is a photosensitive layer. The dissolution rate of the first layer in a developer is less than the dissolution rate of the second layer in the developer.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: November 16, 2021
    Assignee: Fujifilm Electronic Materials U.S.A., Inc.
    Inventors: Sanjay Malik, Raj Sakamuri, Ognian N. Dimov, Binod B. De, William A. Reinerth, Ahmad A. Naiini
  • Patent number: 11137675
    Abstract: A method includes clamping a mask on a mask stage, in which the mask includes a multilayered magnetic film; performing a first lithography process by using the mask; moving the mask away from the mask stage; and determining whether a surface condition of a surface layer of the multilayered thin film is acceptable; and peeling the surface layer of the multilayered magnetic film from the multilayered magnetic film when the surface condition of the surface layer is determined as unacceptable.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Hung Liao, Ju-Wei Liao
  • Patent number: 11137681
    Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: James M. Blackwell, Robert L. Bristol, Marie Krysak, Florian Gstrein, Eungnak Han, Kevin L. Lin, Rami Hourani, Shane M. Harlson
  • Patent number: 11106138
    Abstract: The present disclosure provides resist rinse solutions and corresponding lithography techniques that achieve high pattern structural integrity for advanced technology nodes. An example lithography method includes forming a resist layer over a workpiece, exposing the resist layer to radiation, developing the exposed resist layer using a developer that removes an unexposed portion of the exposed resist layer, thereby forming a patterned resist layer, and rinsing the patterned resist layer using a rinse solution. The developer is an organic solution, and the rinse solution includes water.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Wei Wang, Wei-Han Lai, Ching-Yu Chang
  • Patent number: 11092884
    Abstract: Example embodiments relate to masks for extreme-ultraviolet (extreme-UV) lithography and methods for manufacturing the same. An example embodiment includes a mask for extreme-UV lithography. The mask includes a substrate. The mask also includes a reflecting structure that is supported by the substrate in a use face and is reflection-effective for extreme-UV radiation impinging onto the reflecting structure from a side opposite the substrate. Further, the mask includes attenuating and phase-shifting portions that are distributed within the use face that are suitable for attenuating and phase-shifting extreme-UV radiation parts reflected by the mask through the portions such that an upper surface of the mask in the use face, formed partly by the portions on the side opposite the substrate, exhibits height variations at sidewalls of the portions that extend perpendicular to the use face. In addition, the mask includes a capping layer that covers at least the sidewalls of the portions.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: August 17, 2021
    Assignee: IMEC VZW
    Inventors: Jae Uk Lee, Ryan Ryoung Han Kim
  • Patent number: 11086222
    Abstract: A method of manufacturing a semiconductor structure includes providing a substrate and a photoresist over the substrate; placing a mask over the photoresist; exposing the photoresist to a predetermined electromagnetic radiation through the mask; and removing at least a portion of the photoresist exposed to the predetermined electromagnetic radiation. The mask includes a first portion configured to totally allow the predetermined electromagnetic radiation passing through, a second portion configured to partially allow the predetermined electromagnetic radiation passing through, and a third portion configured to block the predetermined electromagnetic radiation, the second portion is disposed between the first portion and the third portion.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: August 10, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Yu-Mei Ni, Shih-Yi Liu
  • Patent number: 11086221
    Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
  • Patent number: 11086220
    Abstract: Underlayer coating compositions are provided that comprise 1) a resin; and a solvent component comprising one or more solvents having a boiling of 200° C. or greater. Coating compositions are particularly useful with overcoated photoresist compositions imaged with EUV.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 10, 2021
    Assignee: Rohm and Haas Electronic Materials Korea Ltd.
    Inventors: Jung Kyu Jo, Jae Hwan Sim
  • Patent number: 11079681
    Abstract: A lithography method includes forming a resist layer over a substrate. The resist layer is exposed to radiation. The exposed resist layer is developed using a developer that removes an exposed portion of the exposed resist layer, thereby forming a patterned resist layer. The patterned resist layer is rinsed using a basic aqueous rinse solution.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hui Weng, Chen-Yu Liu, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 11073763
    Abstract: Shrinkage and mass losses are reduced in photoresist exposure and post exposure baking by utilizing a small group which will decompose. Alternatively a bulky group which will not decompose or a combination of the small group which will decompose along with the bulky group which will not decompose can be utilized. Additionally, polar functional groups may be utilized in order to reduce the diffusion of reactants through the photoresist.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Han Lai, Ching-Yu Chang, Chen-Hau Wu
  • Patent number: 11067726
    Abstract: A manufacturing system for fabricating self-aligned grating elements with a variable refractive index includes a patterning system, a deposition system, and an etching system. The manufacturing system performs a lithographic patterning of one or more photoresists to create a stack over a substrate. The manufacturing system performs a conformal deposition of a protective coating on the stack. The manufacturing system performs a deposition of a first photoresist of a first refractive index on the protective coating. The manufacturing system performs a removal of the first photoresist to achieve a threshold value of first thickness. The manufacturing system performs a deposition of a second photoresist of a second refractive index on the first photoresist. The second refractive index is greater than the first refractive index. The manufacturing system performs a removal of the second photoresist to achieve a threshold value of second thickness to form a portion of an optical grating.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: July 20, 2021
    Assignee: Facebook Technologies, LLC
    Inventors: Matthew E. Colburn, Giuseppe Calafiore, Matthieu Charles Raoul Leibovici, Nihar Ranjan Mohanty
  • Patent number: 11054735
    Abstract: A mask blank having fast repair rate of EB defect repair and high repair rate ratio to EB defect repair relative to a transparent substrate that includes a phase shift film on a transparent substrate, the phase shift film has a structure including three sets or more of a set of a stacked structure including a high transmitting layer and a low transmitting layer, the high transmitting layer and the low transmitting layer are made of a material consisting of silicon and nitrogen, or a material consisting of silicon, nitrogen, oxygen, and one or more elements selected from a metalloid element and a non-metallic element, the high transmitting layer includes 50 atom % or more nitrogen content and has a thickness of 12 nm or less, and the low transmitting layer includes less than 50 atom % nitrogen content and has a thickness less than the high transmitting layer.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: July 6, 2021
    Assignee: HOYA CORPORATION
    Inventors: Takenori Kajiwara, Ryo Ohkubo, Hiroaki Shishido, Osamu Nozawa
  • Patent number: 11048159
    Abstract: A method of manufacturing a reflective mask blank includes: forming a multilayer reflective film, which is configured to reflect EUV light, on a substrate to form a substrate with a multilayer reflective film; subjecting the substrate with a multilayer reflective film to defect inspection; forming an absorber film, which is configured to absorb the EUV light, on the multilayer reflective film of the substrate with a multilayer reflective film; forming a reflective mask blank, in which an alignment region is formed in an outer peripheral edge region of a pattern formation region by removing the absorber film so that the multilayer reflective film of an area including an element serving as a reference of defect information on the multilayer reflective film is exposed in the alignment region; and performing defect management of the reflective mask blank through use of the alignment region.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 29, 2021
    Assignee: HOYA CORPORATION
    Inventors: Tsutomu Shoki, Takahiro Onoue
  • Patent number: 11042094
    Abstract: An object of the present invention is to provide a treatment liquid for patterning a resist film and a pattern forming method, each of which can simultaneously suppress the occurrence of pattern collapse in a resist L/S pattern and the occurrence of omission failure in a resist C/H pattern. The treatment liquid of the present invention is a treatment liquid for patterning a resist film, which is used for subjecting a resist film obtained from an actinic ray-sensitive or radiation-sensitive resin composition to at least one of development or washing, and contains an organic solvent, in which the treatment liquid contains a first organic solvent having a relative dielectric constant of 4.0 or less and a second organic solvent having a relative dielectric constant of 6.0 or more.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: June 22, 2021
    Assignee: FUJIFILM Corporation
    Inventors: Shuji Hirano, Hideaki Tsubaki, Toru Tsuchihashi, Wataru Nihashi, Kei Yamamoto
  • Patent number: 11042093
    Abstract: A method of manufacturing a semiconductor device comprising: providing a semiconductor device substrate having a relief image on a surface of the substrate, the relief image having a plurality of gaps to be filled; applying a coating composition to the relief image to provide a coating layer, wherein the coating composition comprises (i) a polyarylene oligomer comprising as polymerized units one or more first monomers having two or more cyclopentadienone moieties and one or more second monomers having an aromatic moiety and two or more alkynyl moieties; wherein the polyarylene oligomer has a Mw of 1000 to 6000 Da, a PDI of 1 to 2, and a molar ratio of total first monomers to total second monomers of 1:>1; and (ii) one or more organic solvents; curing the coating layer to form a polyarylene film; patterning the polyarylene film; and transferring the pattern to the semiconductor device substrate.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: June 22, 2021
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: James F. Cameron, Keren Zhang, Li Cui, Daniel Greene, Shintaro Yamada
  • Patent number: 11036142
    Abstract: The substrate processing method is a substrate processing method for removing a resist having a hardened layer from a substrate on a surface of which the resist is formed, including: a substrate holding step of holding the substrate; and a resist stripping step of stripping the resist from the surface of the substrate by supplying ozone gas and superheated steam to a plural-fluid nozzle for producing liquid drops through mixing a plurality of fluids to discharge mixed gas of ozone gas and superheated steam containing liquid drops of ozone water produced by mixing ozone gas and superheated steam from the plural-fluid nozzle toward the surface of the substrate.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: June 15, 2021
    Inventor: Kota Sotoku
  • Patent number: 11036129
    Abstract: A method for forming a photomask includes receiving a substrate having a first layer formed thereon, wherein a patterned second layer exposing portions of the first layer is disposed over the substrate, removing the exposed portions of the first layer through the patterned second layer to form a plurality of openings in the first layer, removing the patterned second layer, and performing a wet etching to remove portions of the first layer to widen the plurality of openings with an etchant. The etchant is in contact with a top surface of the first layer and sidewalls of the plurality of openings. Each of the plurality of openings has a first width prior to the performing of the wet etching and a second width after the performing of the wet etching. The second width is greater than the first width.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Yang Huang, Hao-Ming Chang, Ming Che Li, Yu-Hsin Hsu, Po-Cheng Lai, Kuan-Shien Lee, Wei-Hsin Lin, Yi-Hsuan Lin, Wang Cheng Shih, Cheng-Ming Lin