Patents Examined by Kaushik Patel
  • Patent number: 7395372
    Abstract: A system and method for accessing a data cache having at least two ways for storing data at the same addresses. A first and second tag memory store first and second sets of tags identifying data stored in each of the ways. A translation device determines from a system address a tag identifying one of the ways. A first comparator compares tags in the address with a tag stored in the first tag memory. A second comparator compares a tag in the address with a tag stored in the second tag memory. A clock signal supplies clock signals to one or both of the ways in response to an access mode signal. The system can be operated so that either both ways of the associative data cache are clocked, in a high speed access mode, or it can apply clock signals to only one of the ways selected by an output from the first and second comparators in a power efficient mode of operation.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: July 1, 2008
    Assignee: International Business Machines Corporation
    Inventors: Anthony Correale, Jr., James N. Dieffenderfer, Robert L. Goldiez, Thomas P. Speier, William R. Reohr
  • Patent number: 7370154
    Abstract: A method and apparatus for maintaining coherence information in multi-cache systems is described herein. In one embodiment, the apparatus includes an Ingrained Sharing Directory Cache (ISDC) to store state information about recent copies of local memory blocks. The ISDC is adapted to receive Ingrained Sharing Directory Storage (ISDS) requests and create ISDC entries from information presented by the ISDS. The apparatus also includes an ISDC pending queue to store pending ISDC operations.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: May 6, 2008
    Assignee: Silicon Graphics, Inc.
    Inventor: Tomasz Kaczynski
  • Patent number: 7363468
    Abstract: The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: April 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: Brian David Barrick, Kimberly Marie Fensler, Dwain Alan Hicks, David Scott Ray, David Shippy, Takeki Osanai
  • Patent number: 7360017
    Abstract: The present invention provides a storage control device which enables the time between failures to prolong as much as possible, though it uses HDD's whose mean time between failures is relatively short. The storage control device controls spindle motors in a manner that a spindle motor is rotated regarding the HDD of data which can access from a host computer and a spindle motor is stopped regarding the HDD of data which are clearly judged that a host computer does not access the data. Whether the host computers can access the HDD or not is judged by the fact that whether the memory region (internal logical volume) provided by the HDD is in mapped to the host logical volume or not which is recognized by the host computer and is able to access thereby.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: April 15, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Seiichi Higaki, Hisao Honma
  • Patent number: 7356660
    Abstract: A storage device is provided with a file I/O interface control device and a plurality of disk pools. The file I/O interface control device sets one of a plurality of storage hierarchies defining storage classes, respectively, for each of LUs within the disk pools, thereby forming a file system in each of the LUs. The file I/O interface control device migrates at least one of the files from one of the LUs to another one of the LUs of an optimal storage class, based on static properties and dynamic properties of each file.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: April 8, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Naoto Matsunami, Koji Sonoda, Akira Yamamoto, Masafumi Nozawa, Masaaki Iwasaki
  • Patent number: 7350051
    Abstract: A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: March 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: Joaquin Hinojosa, Sheldon B. Levenstein, Bruce Joseph Ronchetti
  • Patent number: 7340494
    Abstract: A garbage collector treats a garbage-collected heap as divided into heap regions, for each of which it maintains a respective remembered set, whose entries list the locations where references located in the heap outside that region refer to references inside that region. The remembered sets are used during space-incremental collection operations on collection sets of those regions; if the garbage collector determines that objects in the collection set are not referred to directly or indirectly from outside the collection set, it reclaims the memory space that they occupy. It places entries into the remembered sets independently of the locations at which the references were found, so any region can be chosen for inclusion in any collection set; no predetermined collection order is required. Instead, the garbage collector performs global marking operations and uses the results to select for collection-set membership the regions that it can most likely collect efficiently.
    Type: Grant
    Filed: November 11, 2004
    Date of Patent: March 4, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: David L. Detlefs, Steven K. Heller, Alexander T. Garthwaite
  • Patent number: 7330950
    Abstract: A storage device is provided with a file I/O interface control device and a plurality of disk pools. The file I/O interface control device sets one of a plurality of storage hierarchies defining storage classes, respectively, for each of LUs within the disk pools, thereby forming a file system in each of the LUs. The file I/O interface control device migrates at least one of the files from one of the LUs to another one of the LUs of an optimal storage class, based on static properties and dynamic properties of each file.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: February 12, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Naoto Matsunami, Koji Sonoda, Akira Yamamoto, Masafumi Nozawa, Masaaki Iwasaki
  • Patent number: 7325093
    Abstract: A recording method includes the steps of reading a management table for managing whether data are recorded on a recording medium in units of a first recording segment; detecting whether the first recording segment is associated with a second recording segment smaller than the first recording segment according to a designation of data recording in units of the second recording segment into the recording medium; discriminating from data in the management table whether it is possible to read data of the first recording segment; reading the data in units of the first recording segment and temporarily recording the data to a memory when in the discriminating step it is determined that it is possible to read data in units of the first recording segment; recording data to a part of the first recording segment recorded in the memory in units of the second recording segment; and recording data of the first recording segment that was temporarily recorded in the memory to the storage medium.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: January 29, 2008
    Assignee: Sony Corporation
    Inventors: Seiji Ohbi, Takashi Kawakami, Manabu Kii, Masato Hattori
  • Patent number: 7305538
    Abstract: The present invention discloses a system for transparent local and distributed memory management. The invention overcomes the prior art's requirement of keeping track of whether a memory space allocated to a new object or a new program or data structure can be reclaimed. According to the present invention an autorelease pool is created at the beginning of a new duty cycle. The autorelease pool retains the newly allocated memory space during the duty cycle. The autorelease pool is automatically disposed of at the end of the duty cycle. As a result of disposing the autorelease pool, the newly allocated memory space is reclaimed (i.e., deallocated). The present invention is useful in distributed networks where different programming conventions on remote and local machines made the prior art's memory management task particularly difficult. The present invention is also useful in an object-oriented programming environment.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: December 4, 2007
    Assignee: Apple Inc.
    Inventors: Blaine Garst, Ali Ozer, Bertrand Serlet, Trey Matteson
  • Patent number: 7296120
    Abstract: Disclosed is an apparatus, method, and program product that provides atomic, multi-word load support without incurring additional memory utilization. A double-word is atomically loaded without the use of one or more additional fields and without a lock. An invalidity marker is used in connection with a cache miss time to ascertain whether a loaded double-word has been stored and loaded atomically, and is thus, valid.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: November 13, 2007
    Assignee: International Business Machines Corporation
    Inventors: Michael Joseph Corrigan, Timothy Joseph Torzewski
  • Patent number: 7287045
    Abstract: A backup method is provided for use with a storage system composed of a memory which stores a control program, a disk drive having an primary volume, a differential volume, and mapping information, the primary volume storing data sent from a client, the differential volume storing differential data of a snapshot of the primary volume, the mapping information managing the relation between data stored in the primary volume and differential data stored in the differential volume, and a control processor which controls read and write of data in the disk drive. The mapping information is referred to compose the data stored in the primary volume and the differential data stored in the differential volume. The composed data is sent to a backup device.
    Type: Grant
    Filed: July 26, 2004
    Date of Patent: October 23, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyuki Saika, Naohiro Fujii
  • Patent number: 7287110
    Abstract: A storage device for a multibus architecture includes at least one memory to store data, information, and/or addresses, along with a memory connection having a port to connect the memory to one of the buses of the multibus architecture. The memory connection, the port, and the bus have data lines to transmit data along with address lines to transmit addresses, and/or control information to control the memory and other devices connected to each specific bus within the multibus architecture. A switching device selectively connects the memory connection to one of the buses to enable a memory access to transmit data, addresses, and/or control information to or from the selected one of these buses.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: October 23, 2007
    Assignee: Micronas GmbH
    Inventors: Ralf Herz, Carsten Noeske
  • Patent number: 7281095
    Abstract: Even if a plurality of tasks that access a plurality of data areas each having the different control method are operated in parallel and the access requests are generated almost simultaneously, the simultaneous accesses to the memory device can be prevented and also a plurality of tasks can be operated in parallel while maintaining a real-time characteristic since the access request contained in the tasks are divided into partial request units by the access-request mediating portion to switch the access requests.
    Type: Grant
    Filed: January 6, 2004
    Date of Patent: October 9, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kouichi Iwamori, Ikuko Fujinawa, Yoshimasa Obayashi, Kenichi Kawaguchi
  • Patent number: 7277978
    Abstract: A memory device driver is described that can support multiple differing memory devices, in particular, differing Flash memory devices, by being internally re-configurable to match the driving and management requirements of the particular memory device. This allows for a limited number of operating system versions to be produced and maintained for a given system by the manufacturer, reducing the possibility of misconfiguration of the system/device by the inadvertent updating or programming of the wrong operating system version by an end user or service personnel. The resulting driver routine and/or operating system is also typically smaller than operating systems/drivers that compile in or load multiple separate drivers into themselves. In one embodiment of the present invention, the software driver is automatically configures itself by querying the memory device for a device ID and/or manufacturer code or by detecting a specific characteristic of the memory device being driven.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: October 2, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Joseph Khatami, Van Nguyen, Wanmo Wong
  • Patent number: 7269694
    Abstract: One embodiment of the present invention provides a system that selectively monitors load instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a load instruction during transactional execution of a block of instructions, the system determines whether the load instruction is a monitored load instruction or an unmonitored load instruction. If the load instruction is a monitored load instruction, the system performs the load operation, and load-marks a cache line associated with the load instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the load instruction is an unmonitored load instruction, the system performs the load operation without load-marking the cache line.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: September 11, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Marc Tremblay, Quinn A. Jacobson, Shailender Chaudhry
  • Patent number: 7269691
    Abstract: A device for managing removable storage media includes a first management unit and a control unit. The first management unit is adapted to update first media management information which is held in said device and which includes at least a first datum that is used to detect that one removable storage medium has been replaced with a second removable storage medium, when the second removable storage medium is connected to said device, the first datum being information other than a user-input password. The control unit is adapted to test a command from an external device for consistency with the first datum and to execute the command if the first datum is consistent with second media management information contained in the command.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: September 11, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shinji Onishi
  • Patent number: 7269693
    Abstract: One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a store instruction during transactional execution of a block of instructions, the system determines whether the store instruction is a monitored store instruction or an unmonitored store instruction. If the store instruction is a monitored store instruction, the system performs the store operation, and store-marks a cache line associated with the store instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the store instruction is an unmonitored store instruction, the system performs the store operation without store-marking the cache line.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: September 11, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Marc Tremblay, Quinn A. Jacobson, Shailender Chaudhry
  • Patent number: 7260672
    Abstract: A destructive-read memory is one that the process of reading the memory causes the contents of the memory to be destroyed. Such a memory may be used in devices that are intended to acquire data that may have associated usage restrictions, such as an expiration date, usage count limit, or data access fee for the acquired data. Typically, to enforce usage restrictions, and protect against theft, complex and often costly security techniques are applied to acquired data. With destructive-read memory, complex and costly security is not required for stored data. In one embodiment, a write-back mechanism, which may employ security, is responsible for enforcing usage restrictions. If the write-back mechanism determines continued access to acquired data is allowed, then it writes back the data as it is destructively read from the memory.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: August 21, 2007
    Assignee: Intel Corporation
    Inventor: John Garney
  • Patent number: 7260699
    Abstract: Computer systems having a plurality of storage systems could not detect addition of storage systems or configuration changes thereof and automatically redistribute existing volumes based on “hints” provided when the volumes were created. A management computer, which is connected via a network to storage systems having volumes connected via a network to a host computer and which stores data used by the host computer, keeps correspondences between levels indicating specific performances of volumes and storage system characteristics indicating performances of the storage systems. From a first storage system, a level is obtained indicating a performance of a volume of the first storage system allocated to the host computer. The storage system characteristics of the first storage system corresponding to the obtained level indicating the performance of the volume, and storage system characteristics of another storage system are referenced, and the performances of the volumes of the storage systems are compared.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: August 21, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Hirotaka Nakagawa, Masayuki Yamamoto, Yasunori Kaneda