Abstract: Systems and methods for performing multi-threaded backups and restores. In one embodiment, a log is maintained to record the source of write commands, and the order in which blocks of data are written to a sequential storage device. The source identification of the write command may consist of such identifiers as a protocol dependent Host ID, the extended-copy-specification-defined List ID, a time stamp, and the size of the backup medium block written. The order in which the data is written to the backup medium can be identified with these same Host ID and List ID numbers. When it is desired to restore data corresponding to one of the threads, the desired blocks of data can be identified in the log, and the preceding blocks stored on the backup medium can be skipped.

Abstract: A method comprising receiving a write request; adding the write request to a batch of substantially contiguous disk writes; determining to write the batch of substantially contiguous disk writes to a non-volatile memory; writing the batch of substantially contiguous disk writes to the non-volatile memory; sending a confirmation of writing the batch of substantially contiguous disk writes; receiving a confirmation of the confirmation of writing; and clearing the batch of substantially contiguous disk writes.

Abstract: Computer systems having a plurality of storage systems could not detect addition of storage systems or configuration changes thereof and automatically redistribute existing volumes based on “hints” provided when the volumes were created. A management computer, which is connected via a network to storage systems having volumes connected via a network to a host computer and which stores data used by the host computer, keeps correspondences between levels indicating specific performances of volumes and storage system characteristics indicating performances of the storage systems. From a first storage system, a level is obtained indicating a performance of a volume of the first storage system allocated to the host computer. The storage system characteristics of the first storage system corresponding to the obtained level indicating the performance of the volume, and storage system characteristics of another storage system are referenced, and the performances of the volumes of the storage systems are compared.

Abstract: In a memory apparatus, there are provided a mirror primary LU which is a memory region on a plurality of storage media formed of nD+1P, a mirror secondary LU that is a memory region on a plurality of storage media formed of mD+1P, an n-RAID control subprogram for performing RAID control of nD+1P, an m-RAID control subprogram for performing RAID control of mD+1P, and an LU mirror subprogram for performing writing into the mirror primary LU and mirror secondary LU and then effectuating duplexing or “mirroring” when a computer issues a data write request. The “m” and “n” are different integers more than or equal to 2.

Abstract: A method and apparatus for input data selection for content addressable memory. In one embodiment, the apparatus includes an array of CAM cells, a select circuit adapted to generate a plurality of select signals each indicative of a segment of input data provided to the CAM apparatus, and switch circuitry including a plurality of programmable switch circuits each programmable to output a respective bit of the input data as a comparand bit for the array of CAM cells in response to one of the select signals.

Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Abstract: Methods and apparatus for determining which of a plurality of physical blocks associated with a logical block is more recently associated with the logical block are disclosed. According to one aspect of the present invention, a method for resolving associations of a first physical block and a second physical block to a logical block associated with a non-volatile memory system includes obtaining a first identifier associated with the first physical block and obtaining a second identifier associated with the second physical block. The identifiers are compared to ascertain whether the first identifier indicates that the first physical block is more recently associated with the logical block. The method also includes completing an operation arranged to provide contents associated with the logical block to the first physical block when it is determined that the first identifier indicates that the first physical block is more newly associated with the logical block.

Abstract: A data processing apparatus 2 is provided which is responsive to data access instructions to perform data access operations. These data access instructions have a first form utilising a 12-bit offset field but with a fixed addressing mode and a second form utilising a shorter 8-bit offset field but with an addressing mode specified within a manipulation mode control field of the data access instruction.

Abstract: A method and apparatus for adaptive multiple line prefetching. In one embodiment, the method includes the identification of a prefetch depth. As described herein, a prefetch depth may refer to a number of memory lines to be prefetched to temporary (cache) memory. Once the prefetch depth is identified, prefetching is performed according to the identified prefetch depth. During the prefetching, the prefetching is adjusted as changes in the prefetch depth are detected. Accordingly, the dynamic adaptive multi-line prefetching mechanism described herein promotes higher system performance by the use of a more efficient prefetching mechanism.

Abstract: An apparatus and a system, as well as a method and article, may operate to map, by an operating system, a range of virtual addresses to a range of physical addresses, wherein a subset of the range of virtual addresses is identity-mapped to a subset of the range of physical addresses. This range of addresses can then be used by heavy data transfer applications in conjunction with a DMA engine to transfer data between memories, or between memory and input/output devices.

Abstract: A system may include several nodes coupled by in inter-node network. Each node includes several active devices coupled by an address network. The address network included in one of the nodes may be configured to convey address packets specifying a particular coherency unit in broadcast mode. The address network included in a different one of the nodes may be configured to convey address packets specifying that coherency unit in point-to-point mode.

Abstract: Disclosed is an information processing system including a first information processing apparatus having a first communication port for transmitting and receiving data; a second information processing apparatus having a second communication port for transmitting and receiving data; and a communicating portion for executing bi-directional communication between the first communication port and the second communication port, the information processing system comprising a utilizing portion for utilizing the communicating portion, for communication in a direction for which a first application program run on the first information processing apparatus sets the first communication port and the second communication port respectively as the sender and the destination of data; and a utilizing portion for utilizing the communicating portion, for communication in a direction for which a second application program run on the second information processing apparatus sets the second communication port and the first communicati

Abstract: A memory controller that includes an interface to a first memory and an interface to a bus coupling the memory controller to at least one processor. The controller also includes circuitry, responsive to read and write commands received over the bus from the at least one processor, to shift data by an amount identified by at least some of the read and write commands.

Abstract: Embodiments of the invention provide an automatic address generator that generates an address sequence directly using counters that count between predefined start and stop values in accordance with a predefined modes of indexing. The counters support slipping when counting to support convolutional filters in one-dimension (1D) and two-dimension (2D). For 2D indexing, a first counter indexes in the X direction and a second counter indexes in the Y direction in memory. The values from the first and second counter are combined with an offset value to form an address directly to memory.

Abstract: A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored.

Abstract: A specialized memory chip which includes an embedded application specific signal processing unit ASSPU. The ASSPU handles one or more predetermined tasks instead of a main processing unit. The ASSPU and the main processing unit can access memory on the memory chip simultaneously.

Abstract: Circuits and methods are provided that alleviate overloading of the command address bus and limit decreases in command address bus bandwidth to allow increased numbers of memory modules to be included in a computer system. A plurality of switches is coupled between the command address bus (which is coupled to the memory controller) and a respective plurality of memory modules. Each switch provides command address bus data only to its respective memory module. Preferably, only one switch does so at a time, limiting the loading seen by the memory controller.

Abstract: A method of managing memory mapped input output operations to an alternate address space comprising: executing a first instruction directed to a first memory mapped input output alternate address space of a machine associated with a first adapter to allocate a resource associated with the first adapter to a process in accordance with a definition of a z/Architecture; wherein a selected process issues at least one of a load and a store instruction executed in a problem state of the machine to a selected address location of a selected resource. The method further includes ensuring that the selected resource corresponds with the allocated resource and determining that the selected process corresponds with the process to which the resource is allocated.

Abstract: A user visiting a space is equipped with a mobile device in communication with a service system. Media items held by the service system are associated with various locations around the space and a user arriving at such a location is presented with the corresponding item or items. These media items are pre-emptively loaded into a cache of the user's mobile device in dependence on the user's progress around the space. Items can also be flushed from cache on this basis.

Abstract: In a single-chip microcomputer including a nonvolatile semiconductor memory device and write, read and erase circuits for performing a write operation, a read operation and an erase operation upon the nonvolatile semiconductor memory device, respectively, a sequencer is connected between the write, read and erase circuits and an interface. The sequencer receives first data via the interface from the exterior to write the first data into the nonvolatile semiconductor memory device, reads the first data from the nonvolatile semiconductor device, compares the first data with second data read via the interface from the exterior thus performing a verification upon the nonvolatile semiconductor memory device, and reads third data from the nonvolatile semiconductor memory device and transmits the third data via the interface to the exterior.