Abstract: There are method and apparatus for driving a liquid crystal display apparatus which has a liquid crystal and electrodes arranged in a matrix form and in which a number of pixels having a memory effect are provided. Image information is displayed by a refresh scanning by using the liquid crystal display apparatus and is displayed by a non-refresh scanning without substantially changing the image information displayed by the liquid crystal display apparatus. A signal to fluctuate a transmission light amount of the pixel is applied to the electrode during the execution of the display by the non-refresh scanning. A smectic liquid crystal or a ferroelectric liquid crystal is used as a liquid crystal.

Abstract: A graphic display processing apparatus which includes a CPU, a VRAM and a display controller, a data operation unit, an access cycle generator, an address generator and a sequential transfer sequencer. The graphic display processing apparatus also includes a mask pattern generator, dot mask generator and data position transformer. In the graphic display process apparatus block transfer and character drawing are reformed at high speeds, thereby making a window system more practical and offering comfortable operational environment to the user.

Abstract: Broadband coherent and incoherent interfering signals (jammers) are suppressed by using differencing and summing operations in an adaptive signal processing array composed of a plurality of signal detectors. A number of variable weight adaptive filters, equal to or greater than the number of jammers, are applied to all but one of the difference signals. The weighted difference signals are summed and subtracted from the remaining delayed difference signal for processing by an unconstrained adaptive algorithm to adjust the variable weights of the filters. The plurality of detector signals are also grouped by overlapping summing operations to produce summed signals for which all but one are applied to simple filters with the same weighting. These weighted summed signals are themselves summed and subtracted from the remaining delayed summed signal for delivery to a conditioning filter to recover the undistorted desired (target) signal.

Abstract: A discriminator discriminates between stationary and non-stationary signals. The energy E(T.sub.i) of the input signal is calculated in a number of windows T.sub.i. These energy values are stored in a buffer, and from these stored values a test variable V.sub.T is calculated. This test variable comprises the ratio between the maximum energy value and the minimum energy value in the buffer. Finally, the test variable is tested against a stationarity limit .gamma.. If the test variable exceeds this limit the input signal is considered non-stationary. This discrimination is especially useful for discriminating between stationary and non-stationary background sounds in a mobile radio communication system.

Abstract: A video register interface for a video processor in which each frame register has a first storage element which is written by a microprocessor interface independently from a second storage element which outputs control data to video processing circuitry. Since reading and writing are done independently to different storage elements, the contents of the register can be changed without adverse effects on a displayed image. The register interface is used in a CMOS video processor which in turn is used in a microprocessor based multimedia computing system.

Abstract: A computer method and system tiles display windows on a computer screen in a fashion that approximately maintains the relative position and size of the display windows as they were before being aligned. Each display window on the computer screen is assigned to a line based on a location of the display window to create one or more linear sections of display windows. The linear sections are arranged to span the computer screen. The display windows assigned to each linear section are arranged to fill the linear section. In one embodiment, the linear sections are horizontal rows and in another embodiment the linear sections are vertical columns.

Abstract: A computer-implemented method and apparatus that automates the entry, modification, and verification of timing diagrams for electrical circuits. The computer-implemented method and apparatus also provides an automated mechanism for analyzing these timing diagrams and verifying that the timing relationships specified for the circuit are met using the parts selected for the circuit.

Abstract: A visually effective image switching apparatus includes a frame memory unit for storing image data for one picture and a decoder for expanding a compressed image data and for outputting the expanded image data. Also included is a graphic memory controller for writing the expanded image data outputted from the decoder directly in the frame memory unit. An I/O access unit is also provided for selecting whether the expanded image data is to be written or not written at the present address of the frame memory. A local bus unit is also provided for transferring the expanded image data to the graphic memory controller. The timing of the decoder, the graphic memory controller and the I/O access unit are controlled by a CPU unit.

Abstract: Front end processors in a graphics architecture execute parallel scan conversion and shading to process individually assigned primitive objects for providing update pixels. A crossbar along with groups of first-in-first-out registers (FIFOs) accommodates data flow to parallel pixel processors with associated memory capabilities (frame buffer banks) where visibility and blending operations are performed on predetermined sequences of update pixels to provide frame buffer pixels and ultimately display pixels. The pixel processors identify with sequences of pixels in the display in patterns designed to equalize processor loads for pixels located along scan lines of a raster, or distributed over an area. Update pixel data is tagged to identify FIFO groups (pixel processors) individual FIFO selection and output sequence. Temporal priority is accomplished so that primitive data is entered in the frame buffer banks (components) restored to the same order as generated at the central processor (CPU) level.

Abstract: A method of input programmed to operate on a representation of a keyboard appearing on a touch-sensitive screen in which letters are made temporarily available to the user based on studies of frequency of occurrence and sequence in the language that may then be selected for input by a sliding motion of an input device. The user slides an input device from the initially selected letter into the area representing any of the temporarily available keys, inputting any of the letters represented thereon. The process of selecting by touch and slide may be repeated as desired by the user. A method of capitalization is provided by touching the screen with an input device on the background area of the keyboard outside of the area representing the key or a letter and then sliding the input device into the area representing the key of the letter.

Abstract: Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

Abstract: A data storage apparatus has a data memory for storing schedule data. The schedule data includes date data, schedule contents data and pictorial symbol data representing schedule contents. When the schedule data is searched, pictorial symbols are read out from the schedule data stored in the data memory and the read-out pictorial symbols are displayed. If one of the displayed pictorial symbols is selected, the schedule data associated with the selected pictorial symbol is read out and displayed.

Abstract: A speech recognition apparatus in which the speech signal is digitalized and subjected to special analysis, word end detection is effected by energy analysis of the speech signal and the recognition system utilizes a Markov model in combination with a neural network learning by specific training steps.

Abstract: A television signal receiving system includes a deinterleaving network (18) containing first and second deinterleaving functions associated with respective memory address controllers (20, 25). One or the other of the deinterleaving functions is selected for use by a multiplexer (30) in response to a Deinterleaver Select control signal. Deinterleaving is accomplished by controlling the read/write addressing of a memory (35) by the selected deinterleaving function.

Abstract: Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

Abstract: A voice-actuated switching system connects one or more microphones to an audio line in accordance with the output signal levels from each of the microphones. To reduce the effects of degradation of speech signals due to reverberation and noise pickup, the switching system uses directional microphones housed in a circular enclosure and arranged in a conference array configuration with response patterns aimed outwardly from the center of the enclosure. The switching system also uses a voting algorithm to select for activation the appropriate microphones indicative of the position of one or more people speaking and a variable weighting factor for gradually turning on or off the signal from each activated microphone that is coupled to the audio line. Typically one microphone will be selected to monitor a person speaking. Since its response pattern is normally pointed in the direction of the person speaking, it is less sensitive to speaker echo due to reverberation.

Abstract: A VLSIC page printer controller includes an instruction processor which responds to a host computer and a printer video processor for accessing data from memory under the control of the instruction processor and serializing data for transfer to a printer through a video port. An I/0 interface interconnects the printer controller with an I/O bus to which is connected a host computer, memory devices, and other peripheral devices. An internal memory interface connects the printer controller to memory, and the printer video processor is provided with direct memory access (DMA). Data and instruction caches and an instruction ROM are provided on-chip. A RISC instruction processing unit includes as an integral part thereof the special function circuits of orthogonal rotator, bit/byte mirror, and pixel modification.

Abstract: A single-chip semiconductor memory device optimized for high performance flat-shaded polygon video systems consists of a RAM with flash fill circuitry whereby the Start and End addresses are specified for a given row; the data within this range are read, modified, and written back to the memory in parallel thereby requiring a maximum of three memory cycles to fill a line segment independent of the length of the line. The data are modified according to a function between a color register and the data already present in the memory array, the functions being: AND, OR, EXCLUSIVE OR, or REPLACE.

Abstract: Overall graphics performance in a computer graphics system is improved by an accelerated interface between high performance microprocessors and hardware adapters which is a combination of hardware and software and which is independent of specific computer languages. The interface was specifically designed for any hardware attached to a central processing unit (CPU) that does not enforce the order of memory accesses. The hardware supported process fools the CPU into thinking that the write and read are accessing the same address, thus guaranteeing that the order of the write and read are correct. In a first method, a hardware pseudo-address are created on the display adapter. When the software writes to the pseudo-address, the display adapter writes the data to the coordinate register. When the software reads from the pseudo-address, the display adapter returns the contents of the actual status address.

Abstract: A method and a device for speech signal digital coding are provided where at each frame there is carried out a long-term analysis for estimating pitch period d and a long- term prediction coefficient b and gain G, and an a-priori classification of the signal as active/inactive and, for active signal, as voiced/unvoiced. Period estimation circuits (LT1) compute such period on the basis of a suitably weighted covariance function, and classification circuits (RV) distinguish voiced signals from unvoiced signals by comparing long-term prediction coefficient and gain with frame-by-frame variable thresholds.