Abstract: An information processing system includes a first memory, a second memory such as a printer buffer capable of a high speed access and independent of the first memory, and an external storage device such as a fixed or hard disk. A first processor primarily uses the first memory as a storage area of information. A second processor primarily uses the second memory as a storage area of information. The second memory and the external storage are selectively used by the first processor auxiliary storage according to the usage status of the first memory and the usage status of the second memory. The second memory is used first as auxiliary storage because of its faster access speeds, and only if the second memory is currently unavailable, is the slower access speed, external storage device used.

Abstract: A distributed animation comprising a plurality of processors wherein each processor is responsible for rendering only a portion of the entire image. After the plurality of processors compute their respective images, the image data is communicated to a buffer. The buffer also receives image data from other sources. The buffer combines the image data from all sources into a single image frame which is then stored in a frame buffer. The buffer comprises a plurality of buffer elements, each buffer element being associated with a single graphics element (processor or video source). Each buffer element includes an input terminal for receiving pixel data from its corresponding graphics element, an output terminal for outputting pixel data, and a second input terminal for receiving pixel data from the output terminal of a previous buffer element. The pixel data typically includes a Z value which provides the depth location in the image of the object represented by that pixel.

Abstract: An arrangement for improved speech comprehension in artificial translation of one language to a second language. The arrangement comprises an analysis unit which carries out an analysis of duration and fundamental tone of the speech in the first language. A prosody-interpreting unit determines, on the basis of the analysis and language-characteristic information, prosody-dependent information in the first speech which is used by a prosody-generating unit for the second language for controlling the speech synthesis. A speech synthesis element thus produces stresses in the speech translated in the second language which, from a language point of view, correspond to stresses in the first language.

Abstract: A data-array processing system with a memory for storing an array of data-elements, a processor to perform a series of operations on data elements stored in a first section (832) of the memory and to copy data from the first section to a second section (830) of the memory after each series of operations, and output hardware, such a video processor and monitor, for outputting the data-elements in the second section. In order to reduce unnecessary copying of data-elements from the first section to the second section, the processor sets flags indicative of each of the of portions (e.g. P, Q, R, S) of the first section which is modified during that processing operation, and checks the flags during the subsequent copying operation to copy only the flagged portions.

Abstract: A method of and a device for speech signal digital coding are described, where spectral parameters are quantized at each frame in order to exploit the actual correlation inside a frame or between contiguous frames. The quantization devices (DQ) recognize strongly correlated signal periods by using a first set of indexes (j.sub.1), representing the parameters and provided by the spectral analysis circuits (ABT, ALT), and in these periods they convert the same indexes into a second set of indexes (j4) which can be coded with a lower number of bits and which is inserted into the coded signal in place of the first set.

Abstract: An input utterance is converted to a sequence of standard or prototype data frames which are compared with word models which are represented by respective sequences of standard or prototype probability states, there being a pre-calculable distance metric representing the degree of match between each prototype data frame and each prototype model state. Only distance measurements better than a calculated threshold are considered meaningful and those meaningful metrics are stored in a packed list. Also stored is an address array of offsets for locating particular meaningful metrics in the list, the address array being accessed by the corresponding frame and state indices. Also stored is an array for distinguishing meaningful and non-meaningful metrics. Accordingly, an input utterance can be evaluated by locating meaningful metrics in the packed list using the address array and by utilizing a default value for any non-meaningful metric.

Abstract: A graphics controller concurrently reads two streams of visual data stored in memory, where one of the streams is in a subsampled data format. The graphics controller upsamples the subsampled visual data and merges the two data streams to generate a merged pixel stream for display. One data stream may be graphics data in an 8-bit CLUT format and the other data stream may be video data in an 8-bit YUV format. The graphics controller may apply chromakeying to generate the merged pixel stream.

Abstract: A system for changing bits of a byte unit individually comprises a data processing unit including specifying circuitry for specifying bit selection information indicative of a predetermined bit in the byte unit, new-data generating circuitry for outputting new data for the predetermined bit, bit changing circuitry including a plurality of data holding circuits respectively for holding individual bits of the byte, gate circuitry receiving, as inputs, the new data and all bits of the byte and, as an enabling input, the bit selection information and transmitting the new data selectively to one of the data holding circuits.

Abstract: A technique for accessing and refreshing memory locations within a plurality of electronic storage devices which need to be refreshed is disclosed. The technique allows for the accessing of memory locations within the plurality of devices row-by-row such that all memory locations having the same row address within each of the devices are accessed before a memory location with a higher row address is accessed. This accessing technique is implemented through the use of a newly designed address decoder architecture. Once data is stored within the memory locations in this manner, the refreshing technique refreshes only those rows within the plurality of devices which contain data.

Abstract: A pixel modification unit is provided for carrying out a variety of raster graphic manipulations in a RISC graphics processor. The pixel modification unit comprises a logic function unit, a masking unit, and a byte mirror unit. The logic function unit can perform any of 16 different logic operations between each bit of a source operand and a destination operand. The source operand may be a bit map fixed data, while the destination operand is pixel data in the bit map corresponding to the graphics image to be modified. The masking unit can mask any or all bits of a destination operand so that the logic function unit does not operate on the masked bits. When masking is implemented, the output of the pixel modification unit is derived from the masked bits from the destination operand and the unmasked bits which were operated on by the logic function unit. The byte mirror unit horizontally reflects a figure in the bit map via reversing the bit order of data bytes retrieved from the bit map.

Abstract: A semiconductor integrated circuit device has a first unit for generating an address and supplying the address to an external device, a plurality of registers for storing predetermined data which designate an address space, a plurality of comparators, and a second unit. Each of the comparators is used to compare the address output from the first unit and the predetermined data stored in each of the registers. The second unit is used to merge a plurality of outputs of the comparators and to generate an enable signal to activate the external device, when at least one of the outputs of the comparators indicates coincidence between the address and the predetermined data. The semiconductor integrated circuit device makes it possible to activate the external device when at least one of the outputs of the comparators indicates coincidence between the address and the predetermined data.

Abstract: A frame buffer designed to be coupled to a data bus and to an output display in a computer system, the frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, address decoding apparatus for controlling access to the array, the address decoding apparatus including column address decoding apparatus for selecting groups of adjacent columns of the array, a plurality of apparatus for selectively writing to each of the columns of any of said groups of adjacent columns, a plurality of color value registers, latching apparatus for storing pixel data equivalent to a row of pixel data to be displayed on the output display, apparatus for writing pixel data from selected groups of adjacent columns of the array to the latching apparatus, and apparatus for connecting either selected ones of the color value registers, the latches, or the data bus to the apparatus for selectively writing to each of the columns of any of said groups of adjacent columns.

Abstract: An interface for a high-performance graphics adapter is provided. A computer system includes a host processor, a coprocessor in the form of a graphics system processor, and memory addressable by both the host and coprocessors. An application computer program running on the host processor utilizes a graphics operating system, such as an Extended Graphics Array Input/Output System (XGA BIOS) to write graphics data in XGA format to the memory. A totally awesome controller translates memory addresses generated by the XGA BIOS (and hence the host processor) into memory addresses recognized by the coprocessor. One or more graphics controllers selectively swap pixel data between Intel order and Motorola order and store the graphics data, into an XGA video-random-access memory (RAM) buffer. A back-end gate array parallel-serial converts input display data in units of designated pixel data, and the graphics data is displayed on a CRT.

Abstract: A video controller uses memory-mapping to address registers in the video controller to enhance speed of the computer system. The memory-map registers may be mapped to a high address area located within the address space of the frame buffer or to a low address area below one megabyte.

Abstract: A video subsystem resides partially on a host processor and partially on a video board. Audio and communications subsystems reside partially on the host processor and partially on a audio/communications board. The video subsystem generates and passes local compressed video signals corresponding to local analog video signals to the communications subsystem. The audio subsystem receives and generates local compressed audio signals corresponding to local analog audio signals to the communications subsystem. The communications subsystem transmits the local compressed video and audio signals over a communications link to a remote computer system. The communications subsystem also receives remote compressed video and audio signals over the communications link from the remote computer system, and passes the remote compressed video and audio signals to the video and audio subsystems, respectively.

Abstract: Digital samples of a voice signal are greatly compressed by filtering the samples to separate the information contained in them into several different frequency bands. In each of a succession of time intervals, the dominant filter output value is identified and converted to floating point form including an exponent and a generally truncated mantissa. All other filter output values for that time interval are also converted to floating point form having the same exponent. The mantissas are then further compressed by grouping values associated with each filter and again converting the mantissas in each group to floating point form having a common local exponent and submantissas. The Walsh-Haddamard transfer is also employed.