Abstract: Methods and systems for periodically analyzing and correcting storage load imbalances in a storage network environment including virtual machines are described. These methods and systems account for various resource types, logical access paths, and relationships among different storage environment components. Load balancing may be managed in terms of input/output (I/O) traffic and storage utilization. The aggregated information is stored, and may be used to identify and correct load imbalances in a virtual server environment in order to prevent primary congestion and bottlenecks.

Abstract: In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.

Abstract: In the described embodiments, a processor captures a value from an element at a key element position in a second input vector into a base value. The processor then generates a result vector by, if the predicate vector is received, for each element in the result vector to the right of the key element position for which a corresponding element in the predicate vector is active, otherwise, for each element in the result vector to the right of the key element position, setting the element in the result vector equal to a result from an associative Boolean operation or a multiplication operation for which the inputs are the base value and a value in each relevant element of a first input vector from an element at the key element position to and including a predetermined element in the first input vector.

Abstract: The described embodiments provide a processor for generating a result vector with summed values from a first input vector. During operation, the processor receives the first input vector, a second input vector, and a control vector. When generating the result vector, the processor first captures a base value from a key element in the second input vector. The processor then writes the sum of the base value and values from relevant elements in the first input vector into selected elements in the result vector. In addition, a predicate vector can be used to control the values that are written to the result vector.

Abstract: The described embodiments provide a processor for generating a result vector with shifted values. During operation, the processor receives a first input vector, a second input vector, and a control vector. When generating the result vector, the processor first captures a base value from a key element position in the second input vector. The processor then determines a number of bit positions to shift the base value using selected relevant elements in the first input vector. The processor then shifts the copy of the base value by the number of bit positions and writes the value into a corresponding element in the result vector. In addition, a predicate vector can be used to control the values that are written to the result vector.

Abstract: A system, and a corresponding method, implemented on a processor, allows for monitoring and control of temporary instant capacity (TiCAP) resources in a computer system. The system includes a resource management system (RMS), which includes a RMS monitor that tracks a workload executing on the computer system and determines when workload demand exceeds allocated non-TiCAP resource capacity, whereby a resource shortfall is generated, and a RMS processor module that compares the resource shortfall to granularity of supply of the TiCAP resources and that generates a TiCAP transfer control request based on the comparison. The system further includes a temporary instant capacity (TiCAP) system that monitors and controls allocation of TiCAP resources on the computer system, and which includes a RMS detection module that receives the request to transfer control of the TiCAP resources to the RMS, and a transfer module that transfers control of the TiCAP resources based on the request.

Abstract: Methods and apparatus relating to instructions with floating point control override are described. In an embodiment, floating point operation settings indicated by a floating point control register may be overridden on a per instruction basis. In an embodiment, at least one of the one or more floating point operation settings is to cause a modification to one of the one or more default settings during execution of the instruction, wherein the second logic is to perform the floating point operation, at least in part, based on the modified default setting. Other embodiments are also described.

Abstract: A method, system, and computer program product for implementing policies in a managed systems environment is provided. A plurality of the heterogeneous entities is organized into a system resource group (SRG). Each of the plurality of heterogeneous entities is visible to an application operable on the managed systems environment. The system resource group is subject to at least one membership requirement, defines a relationship between at least two of the heterogeneous entities, contains at least one policy defining an operation as to be performed on the system resource group for a domain of the managed systems environment, and defines at least a portion of a policy framework between the system resource group and an additional system resource group organized from an additional plurality of the heterogeneous entities. The system resource group expands according to an action performed incorporating the relationship, policy, or policy framework.

Abstract: A processor includes a reconfigurable field of data processing cells. A register is provided where the register has a data stream memory designed to store a data stream and/or parts thereon. The register may be a RAM PAE.

Abstract: A system and method to execute a linear feedback-shift instruction is disclosed. In a particular embodiment the method includes executing an instruction at a processor by receiving source data and executing a bitwise logical operation on the source data and on reference data to generate intermediate data. The method further includes determining a parity value of the intermediate data, shifting the source data, and entering the parity value of the intermediate data into a data field of the shifted source data to produce resultant data.

Abstract: The invention proposes a simple method for controlling distributed functional units (FU) in a system. It offloads the main system processor from intermediate status monitoring. The sequencer controlled system comprises a plurality of functional units, a processor operatively coupled to the plurality of functional units through a bus, a sequencer having a set of registers, and an interrupt source register configured for interrupt polling. The registers are configured to control the timing of at least one operation of the functional units with stored instructions for each of the functional units. The processor sets up at least some of the registers through the bus for the initial configuration and the sequencer is activated by the processor.

Abstract: An HW arithmetic unit executes a predetermined arithmetic operation. An arithmetic-mode determining unit determines, based on an attribute or a content of data relating to processing that has requested the arithmetic operation, either a synchronous mode that executes the processing after waiting for completion of the arithmetic operation by an arithmetic circuit or an asynchronous mode that executes the processing without waiting for completion of the arithmetic operation by the arithmetic circuit, as an execution mode of the arithmetic operation. An arithmetic-process control unit controls the arithmetic operation by the arithmetic circuit according to the determined execution mode.

Abstract: Instead of having a processor with an instruction set architecture (ISA) that includes fixed architected operands, an improved processor supports additional characteristic bits for computing instructions (e.g., a multiply-add, load/store instructions). Such additional bits for the certain instructions influence the processing of these instructions by the processor. Also, a new instruction is introduced for further usage of the proposed method. Typically these additional characteristic bits as well as the instruction can be automatically generated by compilers to provide relatively well-suited instruction sequences for the processor.

Abstract: In one embodiment, the present invention includes a method for accessing registers associated with a first thread while executing a second thread. In one such embodiment a method may include preventing an instruction of a first thread that is to access a source operand from a register file of a second thread from executing if a synchronization indicator associated with the source operand indicates incompletion of a producer operation of the second thread, and executing the instruction if the synchronization indicator indicates completion of the producer operation of the second thread. Other embodiments are described and claimed.

Abstract: In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.

Abstract: An information handling system employs a processor that includes a thread priority controller. An issue unit in the processor sends branch issue information to the thread priority controller when a branch instruction of an instruction thread issues. In one embodiment, if the branch issue information indicates low confidence in a branch prediction for the branch instruction, the thread priority controller speculatively increases or boosts the priority of the instruction thread containing this low confidence branch instruction. In the manner, should a branch redirect actually occur due to a mispredict, a fetcher is ready to access a redirect address in a memory array sooner than would otherwise be possible.

Abstract: A multi-partition computer system provides a configuration inspector for inspecting partitions to determine their identities and configuration information. The system also includes a policy controller for automatically setting workload-management policies at least in part as a function of the configuration information in response to a command. Computer partitions may be inspected to acquire configuration information such as identity and configuration information regarding workload containers contained by each of the partitions. An automatic policy generator may be triggered to generate policies for allocating resources to workloads as a function of the configuration information.

Abstract: The present invention provides a computer implemented method and apparatus to assign software threads to a common virtual processor of a data processing system having multiple virtual processors. A data processing system detects cooperation between a first thread and a second thread with respect to a lock associated with a resource of the data processing system. Responsive to detecting cooperation, the data processing system assigns the first thread to the common virtual processor. The data processing system moves the second thread to the common virtual processor, whereby a sleep time associated with the lock experienced by the first thread and the second thread is reduced below a sleep time experienced prior to the detecting cooperation step.

Abstract: Embodiments of apparatuses, methods, and systems detecting spin loops in a virtual machine environment are disclosed. In one embodiment, an apparatus includes detection logic and virtualization logic. The detection logic is to detect whether a guest is executing a spin loop. The virtualization logic is to transfer control of the apparatus from the guest to a host in response to the detection logic detecting that the guest is executing the spin loop.

Abstract: A method and an apparatus that determine a total number of threads to concurrently execute executable codes compiled from a single source for target processing units in response to an API (Application Programming Interface) request from an application running in a host processing unit are described. The target processing units include GPUs (Graphics Processing Unit) and CPUs (Central Processing Unit). Thread group sizes for the target processing units are determined to partition the total number of threads according to a multi-dimensional global thread number included in the API request. The executable codes are loaded to be executed in thread groups with the determined thread group sizes concurrently in the target processing units.