Abstract: The present invention provides for resource property aggregation. A set of new instances is received from one or more providers. For each new instance in the set of new instances, a determination is made as to whether the new instance represents a same resource as at least one other instance. Responsive to determining that the new instance represents the same resource as another instance, a set of properties associated with the new instance and with the at least one other instance are identified. Each property from the new instance is compared to an associated property in the at least one other instance using a set of precedence rules. At least one property value is identified from either the new instance or the at least one other instance. An aggregate instance is then generated that represents the resource using the identified property values.

Abstract: Computing resource DNA associated with a computing resource of a computing system can be received. The computing resource DNA can include one or more computing resource DNA elements representing identifying characteristics of the computing resource. A set of one or more potential matches for the received computing resource DNA can be ascertained from a set of reference data. When one or more potential matches exist, a confidence factor can be calculated for each potential match. The set of potential matches can then be refined. An optimum match for the computing resource DNA can be determined from the set of refined potential matches. The computing resource DNA can then be identified as a representation of the computing resource associated with the optimum match.

Abstract: A computing method includes specifying a virtual computer system including at least one virtual or physical compute node, which produces data packets having respective source attributes. At least one Virtual Input-Output Connection (VIOC) that is uniquely associated with the values of the source attributes is defined. A policy specifying an operation to be performed with regard to the VIOC is defined. The virtual computer system is implemented on a physical computer system, which includes at least one physical packet switching element. The physical packet switching element is configured to identify the data packets whose source attributes have the values that are associated with the VIOC and to perform the operation on the identified data packets, so as to enforce the policy on the VIOC.

Abstract: A main memory stores cache blocks obtained by dividing a program. At a position in a cache block where a branch to another cache block is provided, there is embedded an instruction for activating a branch resolution routine for performing processing, such as loading of a cache block of the branch target. A program is loaded into a local memory in units of cache blocks, and the cache blocks are serially stored in first through nth banks, which are sections provided in the storage area. Management of addresses in the local memory or processing for discarding a copy of a cache block is performed with reference to an address translation table, an inter-bank reference table and a generation number table.

Abstract: A method, apparatus, and program product share a resource in a computing system that includes a plurality of computing cores. A request from a second execution context (“EC”) to lock the resource currently locked by a first EC on a first core causes replication of the second EC as a third EC on a third core. The first and third ECs are executed substantially concurrently. When the first EC modifies the resource, the third EC is restarted after the resource has been modified. Alternately, a first EC is configured in a first core and shadowed as a second EC in a second core. In response to a blocked lock request, the first EC is halted and the second EC continues. After granting a lock, it is determined whether a conflict has occurred and the first and second EC are particularly synchronized to each other in response to that determination.

Abstract: A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in a firmware hub instructs the northbridge to inhibit an external instruction. In addition, the firmware saves the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU saved on the memory to all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.

Abstract: A shared memory network for communicating between processors using store and load instructions is described. A new processor architecture which may be used with the shared memory network is also described that uses arithmetic/logic instructions that do not specify any source operand addresses or target operand addresses. The source operands and target operands for arithmetic/logic execution units are provided by independent load instruction operations and independent store instruction operations.

Abstract: Re-sequencing commands and data between a master and slave device utilizing parallel processing is disclosed. When utilizing parallel processing while reading and writing data, there is a chance that the data will be read or written in an improper order, given the time delays associated with different slave devices and the processing time associated with various commands. Therefore, to retain the speed and improved performance of parallel processing while maintaining data coherency, the instructions and data are re-sequenced and processed in the proper order, and the returned data are re-sequenced and returned to the processor in the proper order.

Abstract: A method to enforce collaboration rules, in one example embodiment, comprises receiving a request to report a collaboration event to a collaboration workflow, receiving a reported time of the collaboration event, determining an origin of the reported time, updating the reported time with a central time service time when the origin of the reported time is not a central time service, and based on the updated reported time, selectively reporting the collaboration event into the collaboration workflow.

Abstract: A system implemented in hardware includes a main processing core decoding instructions for out of order execution. The instructions include template based user defined instructions. A user execution block executes the template based user defined instructions. An interface is positioned between the main processing core and the user execution block. A computer readable medium includes executable instructions to describe a processing core supporting execution of a proprietary instruction set and decoding of customized instructions that adhere to a specified pattern. The specified pattern includes a source, a destination and a latency period. A user execution block is connected to the processing core to execute the customized instructions.

Abstract: A method for detecting race conditions in a concurrent processing environment is provided. The method comprises implementing a data structure configured for storing data related to at least one task executed in a concurrent processing computing environment, each task represented by a node in the data structure; and assigning to a node in the data structure at least one of a task number, a wait number, and a wait list; wherein the task number uniquely identifies the respective task, wherein the wait number is calculated based on a segment number of the respective task's parent node, and wherein the wait list comprises at least an ancestor's wait number. The method may further comprise monitoring a plurality of memory locations to determine if a first task accesses a first memory location, wherein said first memory location was previously accessed by a second task.

Abstract: A data processing architecture includes an input device that receives an incoming stream of data packets. A plurality of processing elements are operable to process data received from the input device. The input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.

Abstract: Embodiments of an invention for using a processor identification instruction to provide multi-level processor topology information are disclosed. In one embodiment, a processor includes decode logic and control logic. The decode logic is to receive an identification instruction having an associated topological level value. The control logic is to provide, in response to the decode logic receiving the identification instruction, processor identification information corresponding to the associated topological level value.

Abstract: A developer can declare one or more tasks as being replicable. A library manages all tasks that are accessed by an application, including replicable tasks, and further establishes a task manager during requested task execution. During execution, the library generates a plurality of worker threads, and each of the worker threads is assigned to be processed on one of a plurality of different central processing units. When one or more worker threads have finished processing assigned tasks, and other threads are still busy processing other tasks, the one or more idle worker threads copy over and process replicable tasks assigned to the other, busier worker thread(s) to help with processing. The system can also synchronize processing of the replicable task by the plurality of different worker threads and different processors to ensure no processing discrepancies.

Abstract: Parallel data processing systems and methods use cooperative thread arrays (CTAs), i.e., groups of multiple threads that concurrently execute the same program on an input data set to produce an output data set. Each thread in a CTA has a unique identifier (thread ID) that can be assigned at thread launch time. The thread ID controls various aspects of the thread's processing behavior such as the portion of the input data set to be processed by each thread, the portion of an output data set to be produced by each thread, and/or sharing of intermediate results among threads. Mechanisms for loading and launching CTAs in a representative processing core and for synchronizing threads within a CTA are also described.

Abstract: Instruction execution includes fetching an instruction that comprises a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value. It further includes executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test.

Abstract: A microprocessor includes an instruction translator that translates PUSHF, POP, and MOVSB x86 macroinstructions into multiple microinstructions that include a fused store microinstruction. For PUSHF, first and second microinstructions moves the x86 EFLAGS register into and mask off bits in a temporary register, and the fused store microinstruction stores it to a memory location. For POP, a first microinstruction loads a first memory location value into a temporary register and the fused store microinstruction stores it to the second memory location. For MOVSB, the first microinstruction loads a first memory location operand into a temporary register and the fused store microinstruction stores it to a second memory location. A reorder buffer receives the fused store microinstruction into exactly one entry.

Abstract: A method and apparatus are provided for detecting and handling an instruction flush in a microprocessor system. A flush mechanism is provided that is distributed across all of the execution units in a data processing system. The flush mechanism does not require a central collection point to re-distribute the flush signals to the execution units. Each unit generates a flush vector to all other execution units which is used to block register updates for the flushed instructions.

Abstract: A system and method for efficient reliable execution on a simultaneous multithreading machine. A processor is placed in a reliable execution mode (REM) to detect possible errors during execution of a software application. Only two threads may be configured to operate in this mode. Floating-point store and integer-transfer unary instructions may be converted to new instructions. Each new instruction has two source operands, each corresponding to a different thread is specified by a same logical register number as a single source operand of the original unary instruction. All other instructions are replicated, wherein the original instruction and its twin are assigned to different threads. Simultaneous multi-threaded (SMT) floating-point logic may only be able to provide lockstep execution when it communicates using the new instruction with instantiated integer independent clusters.

Abstract: A conditional move instruction implemented in a processor by forming and processing two decoded instructions, and applications thereof. In an embodiment, the conditional move instruction specifies a first source operand, a second source operand, and a third operand that is both a source and a destination. If the value of the second operand is not equal to a specified value, the first decoded instruction moves the third operand to a completion buffer register. If the value of the second operand is equal to the specified value, the second decoded instruction moves the value of the first operand to the completion buffer. When the decoded instruction that performed the move graduates, the contents of the completion buffer register is transferred to a register file register specified by the third operand.