Abstract: A composition comprising a plurality of molecules. Each of the molecules has a core comprising at least one aromatic ring and at least three pendant arms chemically bonded to the core. The pendant arms comprise a phenylene-terminated thiophene oligomer.

Abstract: Disclosed is a semiconductor storage device having a trench around a bit-line diffusion region in an area of a p-well, which constitutes a memory cell area, that is not covered by a word line and a select gate that intersects the word line. An insulating film is buried in the trench.

Abstract: Example embodiments relate to an organic semiconductor polymer, in which fused thiophenes having liquid crystal properties and aromatic compounds having N-type semiconductor properties are alternately included in the main chain of the polymer, an organic active layer, an organic thin film transistor (OTFT), and an electronic device including the same, and methods of preparing the organic semiconductor polymer, and fabricating the organic active layer, the OTFT and the electronic device using the same. This organic semiconductor polymer has improved organic solvent solubility, processability, and thin film properties, and may impart increased charge mobility and decreased off-state leakage current when applied to the channel layer of the organic thin film transistor.

Abstract: A thin film capacitor with a trench structure having a base substance and a pair of electrodes provided on the base substance, and a dielectrode provided between the electrodes. The trench pattern is configured to have a first pattern and a second pattern separate from the first pattern. The first pattern having a plurality of protrusions provided upright at predetermined intervals, and the second pattern separate from the first pattern having a plurality of recesses provided at predetermined intervals, are provided at the side of the base substance where the dielectric film is formed. Trenches are each defined by the outer wall of each protrusion and the inner wall of each recess.

Abstract: After a fabrication process intended to miniaturize semiconductor devices, a surface area of a stack capacitor in a random access memory (RAM) is significantly reduced and capacity thereof is thus decreased, which in turn causes the capacitor not able to function properly. The present invention provides a composite lower electrode structure consisting of an exterior annular pipe and a central pillar having concave-convex surfaces to increase a surface area of the capacitor within a limited memory cell so as to enhance the capacity. To reinforce intensity of a structure of the capacitor, the exterior annular pipe has an elliptic radial cross section and a thicker thickness along a short axis direction.

Abstract: An electronic device comprising a polymer of Formula or Structure (I) wherein R1 is hydrogen, halogen, a suitable hydrocarbon, or a heteroatom containing group; R2 is hydrogen, a suitable hydrocarbon, a heteroatom containing group, or a halogen; R3 and R4 are independently a suitable hydrocarbon, hydrogen, a heteroatom containing group, or a halogen; Ar is an aromatic component; x, y, a, b, and c represent the number of groups or rings, respectively; Z represents sulfur, oxygen, selenium, or NR wherein R is hydrogen, alkyl, or aryl; and n represents the number of repeating units.

Abstract: A semiconductor device of the present invention comprises a logic circuit to which a power supply voltage, a sub-power supply voltage, a ground voltage and a sub-ground voltage are supplied; a driver for generating the sub-power supply voltage and the sub-ground voltage based on the power supply voltage and the ground voltage; a first wiring layer including a sub-power supply line for supplying the sub-power supply voltage and a sub-ground line for supplying the sub-ground voltage; a second wiring layer including source/drain lines for MOS transistors; a third wiring layer including a main power supply line for supplying the power supply voltage and a main ground line for supplying the ground voltage and arranged opposite to the first wiring layer to sandwich the second wiring layer; via structures for connecting the source/drain lines of the second wiring layer to the other layers.

Abstract: Improved thin film transistor array panels are provided. In one embodiment, a panel includes a plurality of gate lines, data lines, and a plurality of switching elements connected to the gate lines and the data lines. An interlayer insulating layer is formed between the gate lines and the data lines. A passivation layer covering the gate lines, the data lines, and the switching elements is also provided having a plurality of first contact holes exposing portions of the data lines, wherein the switching elements and the pixel electrodes are connected through the first contact holes. A plurality of contact assistants are formed on the passivation layer and are connected to the data lines through a plurality of second contact holes in the passivation layer. A plurality of auxiliary lines are connected to the data lines through a plurality of third contact holes in the interlayer insulating layer.

Abstract: This invention pertains to a composition for a dielectric thin film, which is capable of being subjected to a low-temperature process. Specifically, the invention is directed to a metal oxide dielectric thin film formed using the composition, a preparation method thereof, a transistor device comprising the dielectric thin film, and an electronic device comprising the transistor device. The electronic device to which the dielectric thin film has been applied exhibits excellent electrical properties, thereby satisfying both a low operating voltage and a high charge mobility.

Abstract: Embodiments discussed herein relate to processes of producing a field stop zone within a semiconductor substrate by implanting dopant atoms into the substrate to form a field stop zone between a channel region and a surface of the substrate, at least some of the dopant atoms having energy levels of at least 0.15 eV below the energy level of the conduction band edge of semiconductor substrate; and laser annealing the field stop zone.

Abstract: Provided are a semiconductor light emitting device and a method of fabricating the same. The semiconductor light emitting device comprises: a light emitting structure comprising a first conductive type semiconductor layer, an active layer under the first conductive type semiconductor layer, and a second conductive type semiconductor layer under the active layer; a reflective electrode layer under the light emitting structure, and an outer protection layer at an outer circumference of the reflective electrode layer.

Abstract: A semiconductor memory device includes a semiconductor substrate, a semiconductor layer, a source/drain layer, first and second insulating films, and first and second gate electrodes. The semiconductor layer of one conductivity type is formed on a principal surface of the semiconductor substrate. The source/drain layer is formed on the principal surface with being in contact with one end of the semiconductor layer, and has a conductivity type opposite to the one conductivity type. The first insulating film is formed on one side surface of the semiconductor layer. The second insulating film is formed on another side surface of the semiconductor layer. The first gate electrode is formed on the one side surface via the first insulating film. The second gate electrode is formed on the other side surface of the semiconductor layer via the second insulating film, and is opposed to the first gate electrode.

Abstract: A method of manufacturing a semiconductor device involves the steps of: forming a plurality of product formation areas each having a circuit and a plurality of first electrode pads over a main surface of a semiconductor wafer; arranging a plurality of second electrode pads with larger pitches than the first electrode pads in each of the product formation areas; segmenting the semiconductor wafer to separate the plural product formation areas and provide a plurality of semiconductor devices each having the circuit, the plural first electrode pads and the plural second electrode pads on a first surface; and cleaning foreign matter off the first surface of the semiconductor device after the step of segmenting the semiconductor devices.

Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, an insulating layer laminated on the semiconductor substrate, a semiconductor layer laminated on the insulating layer, an annular deep trench having a depth reaching the insulating layer from the surface of the semiconductor layer, a source region formed on the surface layer of the semiconductor layer in a transistor forming region enclosed with the deep trench, a drain region formed on the surface layer of the semiconductor layer in the transistor forming region, an isolation region formed between the source region and the drain region for electrically isolating the source region and the drain region from each other, and a current path formed on the transistor forming region for guiding a current from the drain region to a position opposite to the source region in the vertical direction perpendicular to the surface of the semiconductor device.

Abstract: The semiconductor device includes a substrate having a conductive layer formed on its surface. The conductive layer has a columnar semiconductor formed thereon. The columnar semiconductor has an insulating layer formed therearound. The insulating layer has an electrode film formed therearound. The electrode film functions as an gate electrode of a transistor. The electrode film includes an laminate of two or more conductive films having different work functions.

Abstract: A light emitting device package and a method of manufacturing the light emitting device package are provided. A base is first provided and a hole is formed on the base. After a light emitting portion is formed on the base, a mold die is placed on the light emitting portion and a molding material is injected through the hole. The mold die is removed to complete the package.

Abstract: A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation region of a substrate comprising a semiconductor layer laminated while including a semiconductor layer having a heterojunction on a semiconductor substrate. The device separation region is composed of a layer in which a conductive impurity is introduced, and an electrode to which a positive voltage is to be applied is formed on the device separation region, specifically on the surface of at least a part of the device separation region in the periphery of the field effect transistor.

Abstract: A lamp type light emitting device for safety fuse, including a substrate, an electrode layer, a chip set, a wire set, two leads and an encapsulator. The electrode layer is arranged on the substrate and includes a first T-shaped electrode, a second T-shaped electrode, a first stripe electrode and a second stripe electrode. The chip set includes a first resistor chip and a first light emitting chip arranged on the first T-shaped electrode and a second resistor chip and a second light emitting chip arranged on the second T-shaped electrode. The wire set has fuse wires electrically connected the first resistor chip, the first light emitting chip, the first stripe electrode, the second resistor chip, second light emitting chip, and the second stripe electrode. The leads are electrically connected to the first and the second T-shaped electrodes. The encapsulator encapsulates the electrode layer, the chip set and the wire set.

Abstract: Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

Abstract: An organic semiconductor light-emitting device having the form of a field-effect transistor and a display using this device is provided. In the device, electrons and holes can be transported. The device comprises an organic semiconductor light-emitting layer capable of emitting light by recombination of holes and electrons, a hole injection electrode for injecting holes into the organic semiconductor light-emitting layer, an electron injection electrode for injecting electrons into the organic semiconductor light-emitting layer, and a gate electrode so disposed as to be opposed to the organic semiconductor light-emitting layer between the electrodes. When a control voltage is applied to the gate electrode, the carrier distribution in the organic semiconductor light-emitting layer is controlled. Thus, the light emission can be turned on/off and the emission intensity can be modulated.