Abstract: In a computing system having a multi-core central processing unit (CPU) having at least two cores, it is determined that a task to be scheduled meets clock acceleration criteria such as requiring a number of threads less than or equal to a pre-defined threshold and/or having tasks that will run above a pre-determined amount of time. Thereafter, a clock speed of a first core of the CPU is increased and a clock speed of a second core of the CPU is decreased. Once the clock speeds have been adjusted, the task is scheduled to be executed by the first core. Related apparatus, systems, techniques and articles are also described.

Abstract: The microprocessor which processes instructions with commit conditions in parallel includes a sequential register file for storing result data of sequential instructions; a shadow register file for storing result data of speculative instructions; a TF register including a plurality of entries each holding information indicating that the commit condition is "true", "false" or "undetermined"; an execution control circuit for comparing the commit condition and a corresponding entry in TF register, storing the result data in sequential register file if the instruction is sequential, and storing the result data in shadow register file if the instruction is the speculative; and a commit control circuit for storing the commit condition and transferring the result data stored in the shadow register file to sequential register file when a coincidence is found between true/false for the commit condition and true/false in TF register 10.

Abstract: Method and means are provided for simulating a contiguous data space within a computer memory, and for placing and accessing data objects of various sizes within the simulated contiguous data space. Multiple, sub-data spaces are concatenated in such a way that each page and each sub-data space in the contiguous data space are uniquely identified. Data objects are placed in the contiguous data space and at the first reference to a page of the data object, only the segment containing the referenced page in the contiguous data space is mapped to the database storage disk. Once a data space page is mapped, the operating system can read the page into memory without requesting a disk operation from the database manager. On modifying a page, if the database disk page location is changed, the contiguous data space page is remapped without changing the page address in the data space.

Abstract: An operator of a digital computer system issues a series of operational commands to respective concurrently executing application programs. Each application program includes a client executive routine that records the application program's operational commands and an associated time stamp indicating when the operational command was received from the operator. The operational commands and the time stamps are transferred to a core executive program that records a script of the operational commands. The core executive determines from the time stamps a global sequence in which the operator issued the operational commands to the application programs. In a playback mode, the computer system re-executes the application programs by issuing the operational commands from the script memory to the application programs in the determined global sequence. In a preferred embodiment, the core executive determines a sequence identifier for each operational command.

Abstract: The present invention is directed to a system and method for selecting instruction words from a memory system for simultaneous execution in an execution unit of a computer system. In one example, an instructor selector unit of the present invention employs an addressing unit to fetch instructions from an instruction cache. The instructor selector unit also employs a receiver unit for buffering and transferring multiple aligned as well as misaligned instructions. The instruction selector unit supplies these instructions to an instruction execution unit (having an integer unit and a floating point unit), which is capable of executing two bundled instructions simultaneously. The instruction selector unit can provide instructions to the instruction execution unit individually, or as a bundled pair.

Abstract: The invention is a method and apparatus for verifying compatibility between components of a system which share a client-provider relationship. Briefly, according to the invention, a current version of a provider and a compatibility range are defined for each of a version of a client and a version of a provider. A version of a provider specifies an oldest implementation provider and an oldest definition provider. When a client is linked with a particular version of a provider it stores an identification for that provider, a current indicator for that version of the provider, called a definition provider, and the oldest implementation provider. At runtime, compatibility checks are performed between a client and available versions of the provider(s), called implementation providers, with which it has been linked. For each available version of each type of provider compatibility exists with the client in three situations.

Abstract: A system for retrieval of documents in a client-server environment is disclosed. The system provides compatibility between an attribute based document display system and diverse query languages within remote document repositories. The system includes a local process running on a client module, and a remote process running within each document repository. Each remote process is designed for the particular model of computer used for the server. Each remote process executes a System Query Language (SQL) used by a particular database program running on the server. A particular server may have several database programs implemented thereon, and each database program has a dedicated remote process, where the remote process is matched to the particular database program. The local process on the user's workstation launches inquiries in a first format on the network. Each remote process receiving an inquiry translates the received inquiry into the System Query Language required by its server and its database program.

Abstract: A disk drive stores multimedia data in long spiral data tracks. The tracks on opposite surfaces of the disk spiral in opposite directions, so that a track on one surface can be read as the actuator sweeps in, and a track on the opposite surface can be read as the actuator sweeps out. Because the actuator only follows spiral tracks without performing long seek operations, the actuator motor can be reduced in size and stresses on actuator bearings and other parts are reduced. Additionally, due to reduced disturbances associated with seeks, it is possible to follow tracks more closely and therefore reduce the width of individual tracks. Further cost reductions are accomplished by spinning the disks at a slower speed and reducing the size of the spin motor accordingly. Finally, data density can be increased simply because multimedia data does not require the same low error rate as conventional data. Preferably, a group of disk drives optimized for multimedia data is used to form a video-on-demand system.

Abstract: Method and means are provided for simulating a contiguous data space within a computer memory, and for placing and accessing data objects of various sizes within the simulated contiguous data space. Multiple, sub-data spaces are concatenated in such a way that each page and each sub-data space in the contiguous data space are uniquely identified. Data objects are placed in the contiguous data space and at the first reference to a page of the data object, only the segment containing the referenced page in the contiguous data space is mapped to the database storage disk. Once a data space page is mapped, the operating system can read the page into memory without requesting a disk operation from the database manager. On modifying a page, if the database disk page location is changed, the contiguous data space page is remapped without changing the page address in the data space.

Abstract: Any two of multiple processor elements are coupled with each other via a data communication network that has a definite communication buffer length and includes multiple communication buffers. A packet having a header and body is created using processed data, and then transferred by a transmitting unit. After sending the processed data, the transmitting unit transmits dummy data, having a body which is longer than the communication buffer length in the data communication network, to the same receiving station as the one to which the processed data is transmitted. The transmitting unit then guarantees a processor element serving as a receiving station the arrival of preceding processed data and the header. Control data representing cache invalidation waiting is embedded in the header of the dummy data.

Abstract: An automated operation machine including a first device driver for transmitting a console display message given by being addressed from a program for automatic operation, and a first adaptor connected to the first device driver, for outputting said console display message in a preselected format, can additionally own automatic operation performance without changing the first device driver by including the below-mentioned arrangements.

Abstract: An apparatus and method increases the speed of processing in an electronic data processing system in which a signal set on a first, higher speed bus is communicated to a second, lower speed bus to execute a data transfer operation between the first, higher speed bus and the second, lower speed bus. The apparatus has means for storing the signal set communicated to the second bus in a first operation and means for detecting whether the next signal set communicated to the second bus for a second operation is the same as in the first operation. A state machine is operatively connected to the first and second buses for receiving dock signals from the first bus. The state machine is responsive to the clock signals to transition from an idle state to at least one set-up state in which a data transfer setup operation occurs and to a further state in which a data transfer is executed.

Abstract: Method and means are provided for simulating a contiguous data space within a computer memory, and for placing and accessing data objects of various sizes within the simulated contiguous data space. Multiple, sub-data spaces are concatenated in such a way that each page and each sub-data space in the contiguous data space are uniquely identified. Data objects are placed in the contiguous data space and at the first reference to a page of the data object, only the segment containing the referenced page in the contiguous data space is mapped to the database storage disk. Once a data space page is mapped, the operating system can read the page into memory without requesting a disk operation from the database manager. On modifying a page, if the database disk page location is changed, the contiguous data space page is remapped without changing the page address in the data space.

Abstract: Processes and devices for enhancing communication management and control in an intelligent network. A Service Management System Information Model serves as the basis for generation of Network Element Images which facilitate data communication between the Service Management System and the various Network elements. The Service Management System Information Model also allows a more intuitive and efficient provisioning interface for the Service Management System user. Network Element Interfaces according to the present invention contain embedded Service Management System/Network Element Interface Protocol functionality and may be employed to interpret the Network Element Images and communicate them over the network to the Network Elements. A Network Element Interface Server allows requests from client programs in the service management system to be queued and prioritized as desired for further efficiency, flexibility and reliability.

Abstract: A computer system with a coupling facility is provided with a plurality of processors and a plurality of intersystem channels coupled to the processors via a memory bus. The coupling facility includes a memory bus interface for the memory bus and a plurality of channels for coupling said channels to said processors. The memory bus interface includes an adapter with at least two hardware vectors provided for command detection, command isolation, and parallel testing of the error states of the intersystem channels, one which detects a command vector arrival, and a second which contains error state vector indicators. A LOCATE CHANNEL BUFFER (LCB) instruction is employed which performs a sense and reset operation on the command vector to identify and isolate a new command, and subsequently reads a vector of said error states vector indicator to determine the presence or absence of link errors.

Abstract: The invention is a design evaluation apparatus for evaluating a design composed of a plurality of design elements. The apparatus has a database stored therein. The database contains design elements, evaluation terms and a table defining relations of the respective design elements with respect to each of the evaluation terms. At least one of the evaluation terms representative of the design is selected from the table, based upon the design elements of the design. The selected evaluation term is used to produce an evaluation result.

Abstract: A processor core for supporting the concurrent execution of mixed integer and floating point operations includes integer functional units (110) utilizing 32-bit operand data and a floating point functional unit (22) utilizing up to 82-bit operand data. Eight operand busses (30, 31) connect to the functional units to furnish operand data, and five result busses (32) are connected to the functional units to return results. The width of the operand busses is 41 bits, which is sufficient to communicate either integer or floating point data. This is done using an instruction decoder (18) to apportion a floating point operation which operates on 82-bit floating point operand data into multiple suboperations each associated with a 41-bit suboperand. The operand busses and result busses have an expanded data-handling dimension from the standard integer data width of 32 bits to 41 bits for handling the floating point operands.

Abstract: A method is provided which controls a data processing system having two common memories forming a duplex memory, a plurality of clusters provided in common for the common memories, and input/output paths connecting the clusters to the common memories. The method includes the steps of detecting a failure which has occurred in one of the common memories by each of the clusters, physically disconnecting input/output paths connected to the above-mentioned one of the common memories therefrom when the failure is detected by one of the clusters, and inhibiting the clusters from accessing the above-mentioned one of the common memories in which the failure has occurred. There is also provided a data processing system that uses such a method.

Abstract: The present invention provides a configurable architecture for serial communications. The architecture can emulate parallel to serial conversion devices for both synchronous and asynchronous data transmission. The invention uses a plurality of register sets to emulate standard interfaces. One register block performs data and control storage to communicate between a host computer and a local processor. A second register block emulates a serial communications controller (SCC) with its own data control storage and features to implement a number of communication protocols. The SCC provides serial data output. This invention provides an architecture of flexibility optimizing a configuration for synchronous and asynchronous requirements using the same basic blocks while still maintaining an interface compatible with standard requirements.

Abstract: An input/output device comprises a first controller for controlling input/output of information, an interface provided between the first controller and an information exchange unit, and a receiver for receiving data inherent to the interface from the interface. A discriminator discriminates whether data received by the receiver is one registered in the first controller, and a second controller inhibits the exchange of information between the interface and the first controller when the discriminator discriminates that the data received by the receiver is not one registered in the first controller.