Abstract: A processor (10) has two modes of operation. One mode of operation is a normal mode of operation wherein the processor (10) accesses user address space or supervisor address space to perform a predetermined function. The other mode of operation is referred to as a debug, test, or emulator mode of operation and is entered via an exception/interrupt. The debug mode is an alternate operational mode of the processor (10) which has a unique debug address space which executes instructions from the normal instruction set of the processor (10). Furthermore, the debug mode of operation does not adversely affect the state of the normal mode of operation while executing debug, test, and emulation commands at normal processor speed. The debug mode is totally non-destructive and non-obtrusive to the "suspended" normal mode of operation. While in debug mode, the existing processor pipelines, bus interface, etc. are utilized.

Abstract: An instruction accelerator which includes an instruction source, and a single instruction multiple data array processor which executes the instructions supplied by the instruction source. A loop processor identifies all loop type instructions which are supplied by the instruction source, copies those instructions supplied by the instruction source into a loop memory, and supplies those loop instructions to the single instruction multiple data array processor in the order received, at the rate required by the single instruction multiple data array processor, and as many times as required by the loop count field.

Abstract: A processing system and method of operation are provided, In response to a branch instruction, a first instruction is processed so that a storage location is associated with the first instruction prior to execution of the branch instruction. In response to execution of the branch instruction, a second instruction is processed independent of information previously stored in the storage location so that the storage location is associated with the second instruction prior to completion of the branch instruction.

Abstract: In a reconfigurable communications system, circuit status bits are stored in a first matrix of rows associated respectively with predefined network configurations and columns associated, respectively, with predefined circuit configurations. Destination status codes are stored in a second matrix of rows associated respectively with the circuit configurations and columns associated, respectively, with switching nodes of the system. Each circuit configuration comprises one or more transmission links, and each circuit status bit stored in each column of the first matrix pattern indicates the presence or absence of the circuit configuration associated with that column. Each destination status code indicates the presence or absence of transmission links from each switching node to possible destination nodes.

Abstract: Method and system for dispatching a message to an alternate object upon its failure to find a required method at the object to which originally sent. The method and system employ the technique of using alternate dispatch variables which can be provided with values naming the alternate objects to which the messages are to be dispatched upon failure of execution at the local object. The alternate object toward which the message is dispatched may contain a method required for execution by a message sent to a first object, but which is unfulfilled by absence of the desired method in the first object. The class of the first object establishes alternate dispatch variables which can be set at run-time by a user making entries in a graphical user interface (GUI) effective to cause redispatch of the message to the alternate object.

Abstract: In a system for implementing virtual machines a Virtual Machine Monitor (VMM) is assigned an address space separate and distinct from the address space assigned to the virtual machines (VMs). A VM-bit is used to determine whether the processor is executing a process in the VM or the VMM. Through the use of the separate address spaces and the VM-bit a system is disclosed wherein the VMM can take full advantage of all the protection rings offered by the system on which it runs and the VMs are also allowed to operate in an environment that essentially offers the same number of real protection rings as are available on the underlying computer system.

Abstract: A plurality of movies are distributively stored in digitally encoded form on a mass storage unit such as a Redundant Array of Inexpensive Drives (RAID) disk drive array such that they can be viewed on demand by multiple users. A video server receives movie requests from users, and retrieves and transmits the requested movie data from the RAID array to processors at the respective user locations. The processors decode the retrieved data to produce video picture and audio information and display the corresponding movies on monitors. Temporal instantaneous digital data rate signatures for the movies are computed and stored, and a current composite signature is computed by summing the signatures for all movies currently being shown. When an additional movie is requested, the signature for the additional movie is combined with the current composite signature to produce a new composite signature.

Abstract: A system outputs the execution times of an industrial automated apparatus in which, when an instruction interpreting and executing device for interpreting and executing instructions executes each instruction, ID information specifying each executed instruction and time information indicating time at which each instruction is executed are correlated and stored, and execution time of each instruction is calculated, and then outputted, based upon designated ID information and the time information correlated therewith. By virtue of this arrangement, the execution times of desired instructions in an operation program having various steps are outputted accurately in units of the individual instructions.

Abstract: An interconnection topography for microprocessor-based communication nodes consists of opposite arrays of client nodes and resource nodes, with each client node connected to one resource node by a data transfer link, each resource node connected to a resource trunk by a data transfer link, and each node connected to just four neighboring nodes by data transfer links. Communication nodes in the topography are microprocessor controlled, and comprise random access memory and data routing circuitry interfaced to the data transfer links. In one aspect resource nodes are provided with a map of the interconnection topography for use in routing data. In another aspect, individual ones of the communication nodes are programmed as servers for receiving client requests and scheduling routing of resource data.

Abstract: Test vectors for a circuit containing both logic gates and memory blocks are evaluated by applying candidate test vectors to good and faulty versions of the circuit in a computer simulation. The functions of the gates and interconnections in the circuit are stored in memory and the operation of the good and faulty circuits is simulated concurrently. During the simulation, a memory record is created for storing the state of a circuit element in a faulty circuit if the fault is visible at the element. Such records are removed when no longer needed, which speeds up the simulation. A multiprocessor in a pipeline configuration is disclosed for performing the simulation. A first branch in the pipeline simulates the logic gates in the circuit; a second branch simulates the memory blocks.

Abstract: A multiprocessor system containing a networking apparatus and a plurality of processors for transferring data through the networking apparatus from one to another of the plurality of processors. At least one receiving-side processor transmits a transfer allowance signal to the networking apparatus when the processor is ready to receive data, and transmits an on-line/off-line signal to the networking apparatus, where the on-line/off-line signal indicates whether the second processor is in an on-line state or off-line state.

Abstract: An object-oriented architecture for network layer routing is provided which distributes function and system behavior into autonomous router objects. By distributing these functionalities into each object, the services and data normally external to the object are imbedded or accessible within the object itself. In another sense, some objects are distributed across the network; e.g., a separate forwarding engine is provided at each network interface. In a preferred embodiment, each object has: (1) common, protocol-independent functions that are shared by all objects of that class; (2) their own configuration information; (3) accessibility through a router resource object for instantiation and control; (4) automatic persistence in NVRAM; (5) remote management capabilities; and (6) text names for navigation of a resource tree as a file system. These capabilities are in every object regardless of the specific protocol or application.

Abstract: An instruction processor system for decoding compound instructions created from a series of base instructions of a scalar machine, the processor generating a series of compound instructions with an instruction format text having appended control bits in the instruction format text enabling the execution of the compound instruction format text in said instruction processor with a compounding facility which fetches and decodes compound instructions which can be executed as compounded and single instructions by the arithmetic and logic units of the instruction processor while preserving intact the scalar execution of the base instructions of a scalar machine which were originally in storage.

Abstract: A microcontroller fabricated on a semiconductor chip is adapted, when operating, to execute programs and instructions and, in response, to generate control signals to selectively control external apparatus. A clock generates timing signals to control the timing of the microcontroller execution and operation. An on-chip program memory has space avilable for storing a program to be executed by the microcontroller in sequential steps in successive address locations of the program memory. An instruction stored in unerasable memory on the chip initiates self-programming of the program memory with the program to be executed by the microcontroller by enabling a pointer timed by the clock to alternately read addresses containing steps of the program to be executed from off-chip memories and to write same into successive addresses of the on-chip program memory by incrementing the latter addresses with each step to be written therein.

Abstract: A method of routing a requested virtual circuit in a network advantageously uses information about concurrent requests for other virtual circuits. Each virtual circuit request in a set of concurrent requests is specified by one or more parameters and each virtual circuit request is routed as a function of one or more parameters of a plurality of the requests. Thereafter, the routing of each request in the set of requests is refined according to a cost function so that the total cost of routing is reduced.

Abstract: Scalable compound instruction set machine and method which provides for processing a set of instructions or program to be executed by a computer to determine statically which instructions may be combined into compound instructions which are executed in parallel by a scalar machine. Such processing looks for classes of instructions that can be executed in parallel without data-dependent or hardware-dependent interlocks. Without regard to their original sequence the individual instructions are combined with one or more other individual instructions to form a compound instruction which eliminates interlocks. Control information is appended to identify information relevant to the execution of the compound instructions. The result is a stream of scalar instructions compounded or grouped together before instruction decode time so that they are already flagged and identified for selective simultaneous parallel execution by execution units.

Abstract: This is a method of compounding two or more instructions from an instruction stream without knowing the starting point or length of each individual instruction. All instructions include one OP Code at a predetermined field location which identifies the instruction and its length. Those instructions which qualify need to have appropriate tags to indicate they are candidates for compounding. In System 370 where instructions are either 2, 4 or 6 bytes in length, the field positions for the OP Code are presumed based on an estimated instruction length code. The value of each tag based on a presumed OP Code is recorded, and the instruction length code in the presumed OP Code is used to locate a complete sequence of possible instructions. Once an actual instruction boundary is found, the corresponding correct tag values are used to identify the commencement of a compound instruction, and other incorrectly generated tags are ignored.

Abstract: Novel object-oriented client-server facility (CSF) and networking service facility (NSF) interfaces implement communication between application programs residing in client and server nodes of a distributed services network. The CSF interface includes remote procedure call (RPC) objects for invoking and responding to service requests at the nodes, and application programming interface (API) objects for transporting those requests between the nodes. However, the API objects only provide communication transports within a node. Accordingly, the API and RPC objects interact with dynamically-configurable protocol stacks within the NSF interfaces to complete the transport mechanism needed by an application program on the client node when accessing services on a remote server node. A preferred embodiment provides an efficient way to perform object operations in a broadcast fashion over a communication network and ensures the receipt and execution of the operation by each target of the broadcast.

Abstract: A new machine design minimizes latency between many high performance processors and a large amount of shared memory. Wire length, latency and skew are minimized by stacking edge connected modules (ECMs). The ECMs are characterized by signal input/output (I/O) pads on three edges, the two opposing inside connector edges and the third global connector edge. The ECMs support multiple processors per module, a plurality of basic storage modules (BSMs) per module, and portions of request and response switches per module. A plurality of processor ECMs and request switch ECMs are stacked in a first stacks and a plurality of BSM ECMs and response switch ECMs are stacked in a second stack. The two stacks are arranged adjacent one another with the request switch ECMs above or below the processor ECMs and the response switch ECMs below or above the BSM ECMs so that the response switch ECMs are adjacent the processor ECMs and the request ECMs are adjacent the BSM ECMs.

Abstract: A plurality of instructions are read out from an instruction cache 1 for each cycle and temporarily stored in a second shift register SR2. The instructions stored in second shift register SR2 are transferred to empty positions of instruction registers IR0 to IR3 and fetched. An instruction decoder 3 selects instructions which can be processed in a parallel manner from the instructions stored in instruction registers IR0 to IR3 and supplies the same to any of processing units 4 to 7. A selector control circuit 12 controls the selection state of each selector 100 to 103, 200 to 203 based on a NUM signal indicating the number of empty instruction registers. The instructions stored in second shift register SR2 are thereby transferred to emptied instruction registers only. In this way, a new instruction is supplied to an empty instruction register as a supplement for each cycle.