Patents Examined by Kenneth A Parker
  • Patent number: 10700101
    Abstract: A pixel of the display panel includes a first transistor, a second transistor, a first electrode pattern and a second electrode pattern. A first drain of the first transistor is electrically connected with the first electrode pattern. A second drain of the second transistor is electrically connected with the second electrode pattern. The first electrode pattern comprises a first connection portion and a first protrusion. The second electrode pattern comprises a second connection portion and two second protrusions. The second protrusions are respectively connected with two sides of the second connection portion and are extended towards the first connection portion. The first protrusion is connected with the first connection portion and is extended towards the second connection portion and to the location between the second protrusions. The width of the distal end of each of the first protrusion and the second protrusion is smaller.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: June 30, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Meng-Chang Hung, Li-Wei Sung, Chin-Cheng Chien
  • Patent number: 10699951
    Abstract: According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate; a contact region self-aligned to the gate; and a low dielectric constant oxide having a dielectric constant of less than 3.9 located on top of the gate. According to an embodiment of the present invention, a method of forming a self-aligned contact comprises removing at least a portion of an interlayer dielectric layer to expose a top surface of a gate cap located on a substrate; recessing the gate cap to form a recessed area; depositing a low dielectric constant oxide having a dielectric constant of less than 3.9 in the recessed area; and polishing a surface of the low dielectric constant oxide to expose a contact area.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 30, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Balasubramanian Pranatharthiharan, Injo Ok, Charan V. V. S. Surisetty
  • Patent number: 10692866
    Abstract: Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method including performing first fabrication operations to form nanosheet field effect transistor (FET) devices in a first region of a substrate. The first fabrication operations include forming a first channel nanosheet, forming a second channel nanosheet over the first channel nanosheet, forming a first gate structure around the first channel nanosheet, and forming a second gate structure around the second channel nanosheet, wherein an air gap is between the first gate structure and the second gate structure. A dopant is applied to the first gate structure and the second gate structure, wherein the dopant is configured to enter the air gap and penetrate into the first gate structure and the second gate structure from within the air gap.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10692859
    Abstract: An integrated circuit is provided having a semiconductor structure, the semiconductor structure including a vertical field-effect transistor; and a diode wherein the vertical field-effect transistor and the diode are co-integrated in the semiconductor structure.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10679904
    Abstract: A semiconductor structure containing a plurality of stacked vertical field effect transistor (FETs) is provided. After forming a first vertical FET of a first conductivity type at a lower portion of a semiconductor fin, a second vertical FET of a second conductivity type is formed on top of the first vertical FET. The second conductivity type can be opposite to, or the same as, the first conductivity type. A source/drain region of the first vertical FET is electrically connected to a source/drain region of the second vertical FET by a conductive strip structure.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10658027
    Abstract: A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: May 19, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Nhan Do, Xian Liu, Vipin Tiwari, Hieu Van Tran
  • Patent number: 10660159
    Abstract: The invention concerns a transparent heating device comprising: a graphene film fixed to a transparent substrate; a first electrode (205) connected to a first edge of the graphene film; and a second electrode (206) connected to a second edge of the graphene film, wherein there is a resistance gradient across the graphene film from the first electrode (205) to the second electrode (206).
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: May 19, 2020
    Assignees: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, UNIVERSITE GRENOBLE ALPES
    Inventors: Vincent Bouchiat, Laetitia Marty, Nedjma Bendiab
  • Patent number: 10636961
    Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a memory region. The memory region comprises a bottom via, a recap layer on the BV, a bottom electrode on the recap layer, a magnetic tunneling junction layer on the bottom electrode, and a top electrode on the MTJ layer. The material of the recap layer is different from that of the BV.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Hsia-Wei Chen, Hung Cho Wang, Kuei-Hung Shen
  • Patent number: 10622516
    Abstract: An epitaxial structure and a method for making the same are provided. The epitaxial structure includes a substrate, an epitaxial layer and a carbon nanotube layer. The epitaxial layer is located on the substrate. The carbon nanotube layer is located in the epitaxial layer. The method includes following. A substrate having an epitaxial growth surface is provided. A carbon nanotube layer is suspended above the epitaxial growth surface. An epitaxial layer is epitaxially grown from the epitaxial growth surface to enclose the carbon nanotube layer therein. The epitaxial layer is a substantially homogenous material from the substrate.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: April 14, 2020
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 10615259
    Abstract: A semiconductor device may include the following elements: a first doped portion; a second doped portion; an enclosing member, which encloses both the first doped portion and the second doped portion; a first barrier, which directly contacts the first doped portion; a second barrier, which directly contacts the second doped portion; a dielectric member, which is positioned between the first barrier and the second barrier and directly contacts each of the first barrier and the second barrier; a third barrier, which directly contacts the first doped portion; and a device component, wherein a portion of the device component is positioned between the dielectric member and the third barrier.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 7, 2020
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Li Liu, Xianyong Pu, Guangli Yang, Gangning Wang, ChiChung Tai, Hong Sun
  • Patent number: 10601337
    Abstract: A semiconductor device includes a P-type low potential region, an N-type first region, an N-type second region, an N-type third region, an annular trench, and a P-type isolation region. The N-type first region is provided on the principal surface of a P-type SOI layer provided to a P-type SOI substrate. The N-type first region has a concave portion. The N-type third region is provided inside the concave portion of the N-type first region so as to be away from the edge of the concave portion. A level-shift device is formed on the surface of the N-type third region. The P-type isolation region is a slit region extending in U-shape along the boundary between the N-type third region and the concave portion of the N-type first region.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 24, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kan Tanaka
  • Patent number: 10586916
    Abstract: A spin current magnetization reversal element includes: a first ferromagnetic metal layer with a changeable magnetization direction, and a spin-orbit torque wiring, wherein a first direction is defined as a direction perpendicular to a surface of the first ferromagnetic metal layer, the wiring extends in a second direction intersecting the first and is bonded to a first surface of the first ferromagnetic metal layer, wherein the wiring includes a pure spin current generator which is bonded to the metal layer, and a low-resistance portion which is connected to both ends of the generator in the second direction and is formed of a material having a smaller electrical resistivity than the generator, and the generator is formed so that an area of a cross-section orthogonal to the first direction continuously and/or stepwisely increases as it recedes from a bonding surface bonded to the first ferromagnetic metal layer in the first direction.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: March 10, 2020
    Assignee: TDK CORPORATION
    Inventors: Yohei Shiokawa, Tomoyuki Sasaki
  • Patent number: 10573517
    Abstract: A method for depositing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate is provided. Due to the strong adhesion of graphene and cobalt to a semiconductor substrate, the layer of graphene is epitaxially deposited.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: February 25, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Vikas Berry, Sanjay Behura, Phong Nguyen, Michael R. Seacrist
  • Patent number: 10566343
    Abstract: A semiconductor memory device mc des a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventors: Sung-Lae Oh, Jin-Ho Kim, Chang-Man Son, Go-Hyun Lee, Young-Ock Hong
  • Patent number: 10566462
    Abstract: A bipolar semiconductor device and method are provided. One embodiment provides a bipolar semiconductor device including a first semiconductor region of a first conductivity type having a first doping concentration, a second semiconductor region of a second conductivity type forming a pn-junction with the first semiconductor region, and a plurality of third semiconductor regions of the first conductivity type at least partially arranged in the first semiconductor region and having a doping concentration which is higher than the first doping concentration. Each of the third semiconductor regions is provided with at least one respective junction termination structure.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: February 18, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Frank Pfirsch, Franz-Josef Niedernostheide
  • Patent number: 10559501
    Abstract: A method of producing a FinFET device with fin pitch of less than 20 nm is presented. In accordance with some embodiments, fins are deposited on sidewall spacers, which themselves are deposited on mandrels. The mandrels can be formed by lithographic processes while the fins and sidewall spacers formed by deposition technologies.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: February 11, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Song, Jeffrey Xu, Da Yang, Kern Rim, Choh Fei Yeap
  • Patent number: 10559599
    Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: February 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba
  • Patent number: 10546998
    Abstract: Some embodiments include constructions having electrically conductive bitlines within a stack of alternating electrically conductive wordline levels and electrically insulative levels. Cavities extend into the electrically conductive wordline levels, and phase change material is within the cavities. Some embodiments include methods of forming memory. An opening is formed through a stack of alternating electrically conductive levels and electrically insulative levels. Cavities are extended into the electrically conductive levels along the opening. Phase change material is formed within the cavities, and incorporated into vertically-stacked memory cells. An electrically conductive interconnect is formed within the opening, and is electrically coupled with a plurality of the vertically-stacked memory cells.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: January 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: John D. Hopkins
  • Patent number: 10546999
    Abstract: A variable resistance memory device and a method of manufacturing the same, the device including first conductive lines disposed in a first direction on a substrate, each of the first conductive lines extending in a second direction crossing the first direction, and the first and second directions being parallel to a top surface of the substrate; second conductive lines disposed in the second direction over the first conductive lines, each of the second conductive lines extending in the first direction; a memory unit between the first and second conductive lines, the memory unit being in each area overlapping the first and second conductive lines in a third direction substantially perpendicular to the top surface of the substrate, and the memory unit including a variable resistance pattern; and an insulation layer structure between the first and second conductive lines, the insulation layer structure covering the memory unit and including an air gap in at least a portion of an area overlapping neither the fir
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: January 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Masayuki Terai, Dae-Hwan Kang, Gwan-Hyeob Koh
  • Patent number: 10546995
    Abstract: A spin current magnetization reversal element includes: a first ferromagnetic metal layer with a changeable magnetization direction, and a spin-orbit torque wiring, wherein a first direction is defined as a direction perpendicular to a surface of the first ferromagnetic metal layer, the wiring extends in a second direction intersecting the first and is bonded to a first surface of the first ferromagnetic metal layer, wherein the wiring includes a pure spin current generator which is bonded to the metal layer, and a low-resistance portion which is connected to both ends of the generator in the second direction and is formed of a material having a smaller electrical resistivity than the generator, and the generator is formed so that an area of a cross-section orthogonal to the first direction continuously and/or stepwisely increases as it recedes from a bonding surface bonded to the first ferromagnetic metal layer in the first direction.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: January 28, 2020
    Assignee: TDK CORPORATION
    Inventors: Yohei Shiokawa, Tomoyuki Sasaki