Patents Examined by Kenneth A Parker
  • Patent number: 8097937
    Abstract: A leadframe, a housing, a radiation-emitting component formed therefrom, and a method for producing the component includes the leadframe having a mount part with at least one bonding wire connecting area and at least one electrical solder connecting strip into which a separately manufactured thermal connecting part, which has a chip mounting area, is linked. To form a housing, the leadframe is sheathed, preferably, with a molding compound, with the thermal connecting part being embedded such that it can be thermally connected from the outside.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: January 17, 2012
    Assignee: OSRAM AG
    Inventors: Georg Bogner, Herbert Brunner, Michael Hiegler, Günter Waitl
  • Patent number: 7999263
    Abstract: Provided is a semiconductor element including: a semiconductor having an active layer; a gate insulating film which is in contact with the semiconductor; a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer; a photosensitive organic resin film formed on the first nitride insulating film; a second nitride insulating film formed on the photosensitive organic resin film; and a wiring provided on the second nitride insulating film, in which a first opening portion is provided in the photosensitive organic resin film, an inner wall surface of the first opening portion is covered with the second nitride insulating film, a second opening portion is provided in a laminate including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening portion, and the semiconductor is connected with the wiring through the first opening portion and the second opening portion.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: August 16, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Masahiko Hayakawa, Shunpei Yamazaki
  • Patent number: 7977671
    Abstract: The present invention relates to a compound having an oxadiazole ring structure having a substituted pyridyl group connected thereto, represented by the following general formula (1). According to the present invention, it becomes possible to provide an organic compound having excellent characteristic of high stability in a thin film state, and the emission efficiency and durability of conventional organic EL devices can be remarkably improved.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: July 12, 2011
    Assignee: Hodogaya Chemical Co., Ltd.
    Inventors: Tetsuzo Miki, Makoto Nagaoka, Shuichi Hayashi, Yoshio Taniguchi, Musubu Ichikawa
  • Patent number: 7973315
    Abstract: A thin film transistor that does not deform or exfoliate due to thermal or mechanical stress, a flat panel display having the same, and a method manufacturing the same, the thin film transistor including a substrate, a patterned buffer layer disposed on the substrate, a patterned active layer disposed on the buffer layer, a gate electrode insulated from the active layer, and a source electrode and a drain electrode that contact the active layer and are insulated from the gate electrode.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: July 5, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Jae-Bon Koo, Hye-Dong Kim, Min-Chul Suh
  • Patent number: 7968983
    Abstract: Provided is a semiconductor device in which a plurality of chips are packaged without increasing the thickness of the package. A plurality of semiconductor elements (a first and a second semiconductor elements) that are packaged in the semiconductor device are overlaid with each other. Specifically, the first semiconductor element is fixed on the top surface of the first island while the second semiconductor element is fixed on the bottom surface of the second island. Furthermore, each of the islands (a first and a second islands) on which the semiconductor elements are respectively mounted in the present invention provides a structure has an irregular shape, and the islands are overlaid with each other along the sides of the semiconductor element to be mounted.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: June 28, 2011
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventor: Hiroyoshi Urushihata
  • Patent number: 7968898
    Abstract: Provided are a nitride semiconductor light emitting device including a coat film formed at a light emitting portion and including an aluminum nitride crystal or an aluminum oxynitride crystal, and a method of manufacturing the nitride semiconductor light emitting device. Also provided is a nitride semiconductor transistor device including a nitride semiconductor layer and a gate insulating film which is in contact with the nitride semiconductor layer and includes an aluminium nitride crystal or an aluminum oxynitride crystal.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: June 28, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takeshi Kamikawa, Yoshinobu Kawaguchi
  • Patent number: 7964861
    Abstract: A phase change memory includes a volume of phase change material disposed between, and coupled to, two electrodes, with the composition of a region of at least one of the two electrodes or phase change material having been compositionally altered to reduce the programmed volume of the phase change material.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: June 21, 2011
    Assignee: Ovonyx, Inc.
    Inventor: Jim Ricker
  • Patent number: 7960279
    Abstract: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: June 14, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
  • Patent number: 7960786
    Abstract: A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW, wherein at least one of the pre-HVW, the HVW, and the field ring comprises at least two tunnels; an insulation region over the field ring and a portion of the HVW; a drain region in the HVW and adjacent the insulation region; a gate electrode over a portion the insulation region; and a source region on an opposite side of the gate electrode than the drain region.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: June 14, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Huang, Tsung-Yi Huang, Fu-Hsin Chen, Chyi-Chyuan Huang, Chung-Yeh Wu
  • Patent number: 7960916
    Abstract: A method of receiving video data, a control signal, etc. via a non-contact transmission path is adopted, and a receiving circuit for receiving and amplifying a signal is formed on the same insulating substrate as a display device. Thus, there are provided a thin-film transistor which is formed in a semiconductor thin film that is formed on the insulating substrate and crystallized in a predetermined direction, and an inductor for forming an inductive-coupling circuit, which is formed by using an electrically conductive thin film provided on the insulating substrate. The direction of movement of carriers flowing in the thin-film transistor is parallel to the direction of crystallization of the semiconductor thin film, and the inductor and the thin-film transistor are integrated so as to be electrically coupled directly or indirectly.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: June 14, 2011
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventor: Genshiro Kawachi
  • Patent number: 7960719
    Abstract: The invention provides a semiconductor device where data can be written after the production and forgery caused by rewriting of data can be prevented, and which can be manufactured at a low cost using a simple structure and an inexpensive material. Further, the invention provides a semiconductor device having the aforementioned functions, where wireless communication is not blocked by the internal structure. The semiconductor device of the invention has an organic memory provided with a memory cell array including a plurality of memory cells, a control circuit for controlling the organic memory, and a wire for connecting an antenna. Each of the plurality of memory cells has a transistor and a memory element. The memory element has a structure where an organic compound layer is provided between a first conductive layer and a second conductive layer. The second conductive layer is formed in a linear shape.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: June 14, 2011
    Assignee: Semiconductor Energy Laboratotry Co., Ltd.
    Inventor: Kiyoshi Kato
  • Patent number: 7952108
    Abstract: Reducing effects of thermal expansion in electronic components. An electronic device can include a support, such as a leadframe. An electronic component can be supported by the support. A first flexible layer can cover the electronic component. A second more rigid layer can cover the first layer. The first layer can be made from a material that is more flexible than the second layer thereby creating a mechanical buffer layer between the second layer and the electronic component such that the electronic component is protected from thermal expansion of the second portion caused by changes in temperature. The electronic component can be a laser. The first and second materials can be selected to disperse an optical emission from the optical transmitter.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: May 31, 2011
    Assignee: Finisar Corporation
    Inventors: Jose Joaquin Aizpuru, Christopher William Johnson, Bobby Marion Hawkins
  • Patent number: 7952115
    Abstract: A packaged light emitting device includes a substrate, a solid state light emitting device on the substrate, a first generally toroidal lens on the substrate and defining a cavity relative to the solid state light emitting device and having a first index of refraction, and a second lens at least partially within the cavity formed by the first lens and having a second index of refraction that is different from the first index of refraction. The second index of refraction may be higher than the first index of refraction. The lenses may be mounted on the substrate and/or may formed by dispensing and curing liquid encapsulant materials.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: May 31, 2011
    Assignee: Cree, Inc.
    Inventors: Ban P. Loh, Nicholas W. Medendorp, Jr., Bernd Keller
  • Patent number: 7943944
    Abstract: A radiation-emitting thin-film semiconductor component with a multilayer structure (12) based on GaN, which contains an active, radiation-generating layer (14) and has a first main area (16) and a second main area (18)—remote from the first main area—for coupling out the radiation generated in the active, radiation-generating layer. Furthermore, the first main area (16) of the multilayer structure (12) is coupled to a reflective layer or interface, and the region (22) of the multilayer structure that adjoins the second main area (18) of the multilayer structure is patterned one- or two-dimensionally.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: May 17, 2011
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Dominik Eisert, Berthold Hahn, Volker Härle
  • Patent number: 7943453
    Abstract: A semiconductor structure and a method of forming the same. The semiconductor structure includes a semiconductor substrate, a gate dielectric layer on top of the semiconductor substrate. The structure also includes a first metal containing region on top of the gate dielectric layer. The structure also includes a second metal containing region on top of the gate dielectric layer wherein the first and second metal containing regions are in direct physical contact with each other. The structure further includes a gate electrode layer on top of both the first and second metal containing regions and the gate electrode layer is in direct physical contact with both the first and second metal containing regions. The structure further includes a patterned photoresist layer on top of the gate electrode layer.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: May 17, 2011
    Assignee: International Business Machines Corporation
    Inventors: Bernd Ernst Eduard Kastenmeier, Byoung Hun Lee, Naim Moumen, Theodorus Eduardus Standaert
  • Patent number: 7944023
    Abstract: A semiconductor structure includes a silicon substrate layer, a relaxed silicon-germanium layer on the silicon substrate layer and a strained single crystal silicon layer on the silicon-germanium layer. The silicon-germanium layer may include a thickness of 500 angstroms or less. The method for forming the semiconductor structure includes epitaxially forming the silicon-germanium layer and the single crystal silicon layer. The silicon-germanium layer is stressed upon formation. After the single crystal silicon layer is formed over the silicon-germanium layer, an RTA or laser heat treatment process selectively melts the silicon-germanium layer but not the single crystal silicon layer. The substantially molten silicon-germanium relaxes the compressive stresses in the silicon-germanium layer and yields a relaxed silicon-germanium layer and a strained single crystal silicon layer upon cooling.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: May 17, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Min Cao
  • Patent number: 7939413
    Abstract: An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: May 10, 2011
    Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Yung Fu Chong, Zhijiong Luo, Joo Chan Kim, Brian Joseph Greene, Kern Rim
  • Patent number: 7939895
    Abstract: Disclosed herein is a semiconductor device including a semiconductor substrate provided with an N-type FET and P-type FET, with a gate electrode of the N-type FET and a gate electrode of the P-type FET having undergone full-silicidation, wherein the gate electrode of the P-type FET has such a sectional shape in the gate length direction that the gate length decreases as one goes upwards from a surface of the semiconductor substrate, and the gate electrode of the N-type FET has such a sectional shape in the gate length direction that the gate length increases as one goes upwards from the surface of the semiconductor substrate.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: May 10, 2011
    Assignee: Sony Corporation
    Inventor: Katsuhiko Fukasaku
  • Patent number: 7935958
    Abstract: The present invention provides a semiconductor device which has a storage element having a simple structure in which an organic compound layer is sandwiched between a pair of conductive layers and a manufacturing method of such a semiconductor device. With this characteristic, a semiconductor device having a storage circuit which is nonvolatile, additionally recordable, and easily manufactured and a manufacturing method of such a semiconductor device are provided. A semiconductor device according to the present invention has a plurality of field-effect transistors provided over an insulating layer and a plurality of storage elements provided over the plurality of field-effect transistors. Each of the plurality of field-effect transistors uses a single-crystal semiconductor layer as a channel portion and each of the plurality of storage elements is an element in which a first conductive layer, an organic compound layer, and a second conductive layer are stacked in order.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: May 3, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroko Abe, Yuji Iwaki, Mikio Yukawa, Shunpei Yamazaki, Yasuyuki Arai, Yasuko Watanabe, Yoshitaka Moriya
  • Patent number: 7935974
    Abstract: The invention relates to a monolithic white light emitting device using wafer bonding or metal bonding. In the invention, a conductive submount substrate is provided. A first light emitter is bonded onto the conductive submount substrate by a metal layer. In the first light emitter, a p-type nitride semiconductor layer, a first active layer, an n-type nitride semiconductor layer and a conductive substrate are stacked sequentially from bottom to top. In addition, a second light emitter is formed on a partial area of the conductive substrate. In the second light emitter, a p-type AlGaInP-based semiconductor layer, an active layer and an n-type AlGaInP-based semiconductor layer are stacked sequentially from bottom to top. Further, a p-electrode is formed on an underside of the conductive submount substrate and an n-electrode is formed on a top surface of the n-type AlGaInP-based semiconductor layer.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: May 3, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Min Ho Kim, Masayoshi Koike, Kyeong Ik Min, Myong Soo Cho