Patents Examined by Kenneth A Parker
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Patent number: 11894328Abstract: The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.Type: GrantFiled: May 24, 2022Date of Patent: February 6, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Jung-Hsing Chien
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Patent number: 11877469Abstract: A display device may include a display substrate, an encapsulation substrate, and a sealing member. The display substrate may include a pixel defining layer. The sealing member may include a first portion having an inner portion between the display substrate and the encapsulation substrate and overlapping an edge portion of the pixel defining layer and an outer portion extending from the inner portion and located outside the inner portion; and a second portion between the outer portion and the display substrate.Type: GrantFiled: October 10, 2019Date of Patent: January 16, 2024Assignee: Samsung Display Co., Ltd.Inventors: Seung Kim, Junehyoung Park, Jeongwoo Park, Wonsang Park
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Patent number: 11862654Abstract: Various embodiments of the present disclosure are directed towards an image sensor, and a method for forming the image sensor, in which an inter-pixel trench isolation structure is defined by a low-transmission layer. In some embodiments, the image sensor comprises an array of pixels and the inter-pixel trench isolation structure. The array of pixels is on a substrate, and the pixels of the array comprise individual photodetectors in the substrate. The inter-pixel trench isolation structure is in the substrate. Further, the inter-pixel trench isolation structure extends along boundaries of the pixels, and individually surrounds the photodetectors, to separate the photodetectors from each other. The inter-pixel trench isolation structure is defined by a low-transmission layer with low transmission for incident radiation, such that the inter-pixel trench isolation structure has low transmission for incident radiation.Type: GrantFiled: January 15, 2021Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng Yu Huang, Chun-Hao Chuang, Keng-Yu Chou, Wei-Chieh Chiang, Chin-Chia Kuo, Wen-Hau Wu, Hua-Mao Chen, Chih-Kung Chang
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Patent number: 11854950Abstract: The present invention is intended to provide a semiconductor module and a semiconductor device that are compatible with various rated currents. A semiconductor module includes a lead frame, and a semiconductor element joined with the lead frame. The lead frame includes a first joining structure and a second joining structure. The first joining structure includes a void part as a part at which the lead frame does not exist, and the second joining structure includes a void part as a part at which the lead frame does not exist. Each of the first joining structure and the second joining structure has a shape such that one of the first joining structure and the second joining structure complements at least part of the void part of the other assuming that the first joining structure and the second joining structure are overlapped.Type: GrantFiled: September 3, 2021Date of Patent: December 26, 2023Assignee: Mitsubishi Electric CorporationInventors: Hideo Komo, Arata Iizuka, Takeshi Omaru
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Patent number: 11849573Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. The bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region.Type: GrantFiled: September 10, 2020Date of Patent: December 19, 2023Assignee: Micron Technology, Inc.Inventors: Yuichi Yokoyama, Si-Woo Lee
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Patent number: 11832434Abstract: A memory cell includes: a substrate; an active layer spaced apart from a surface of the substrate and extending in a direction which is parallel to the surface of the substrate; a bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate; a capacitor coupled to another side of the active layer and spaced apart from the surface of the substrate; and a word line vertically spaced apart from the active layer and extending in a direction intersecting with the active layer, wherein the word line includes a first notch-shaped sidewall and a second notch-shaped sidewall that face each other.Type: GrantFiled: June 24, 2021Date of Patent: November 28, 2023Assignee: SK hynix Inc.Inventors: Seung Hwan Kim, Dong Sun Sheen, Su Ock Chung, Il Sup Jin, Seon Yong Cha
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Patent number: 11804490Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.Type: GrantFiled: November 23, 2021Date of Patent: October 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joong Gun Oh, Sung Il Park, Jae Hyun Park, Hyung Suk Lee, Eun Sil Park, Yun Il Lee
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Patent number: 11805672Abstract: Provided is a display device that can retard the degradation of light-emitting elements even when the display device is used in a high temperature environment. A display device includes a TFT layer, a light-emitting element layer provided with a plurality of light-emitting elements, a heat dissipating layer, an extraction member, and a thermal insulation layer that insulates the light-emitting elements from external heat. The thermal insulation layer is made from a material containing a first resin in which a metal complex compound having an ammonium salt as a ligand is dispersed. The TFT layer is formed between the heat dissipating layer and the light-emitting element layer. The heat dissipating layer overlaps the light-emitting elements. The thermal insulation layer surrounds the heat dissipating layer. The extraction member is formed to overlap the thermal insulation layer. The heat dissipating layer and the thermal insulation layer are in direct contact with the TFT layer.Type: GrantFiled: July 1, 2022Date of Patent: October 31, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Masanobu Mizusaki, Masakazu Shibasaki
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Patent number: 11791440Abstract: A method of manufacturing a light emitting element includes forming an n-side electrode at a lateral surface of an n-type semiconductor layer so as not to cover a light extraction surface. Using a portion of a silicon substrate left on an n-type semiconductor layer as a mask, an insulating film formed at a lateral surface of a semiconductor layered body is removed, to expose a lateral surface of the n-type semiconductor layer and a lateral surface of a resin layer. An n-side electrode positioned between the lateral surface of the n-type semiconductor layer and the lateral surface of the resin layer and connected to the exposed lateral surface of the n-type semiconductor layer is formed. Thereafter, the portion of the silicon substrate is removed, to expose the n-type semiconductor layer.Type: GrantFiled: June 11, 2020Date of Patent: October 17, 2023Assignee: NICHIA CORPORATIONInventor: Hirofumi Nishiyama
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Patent number: 11765884Abstract: The present disclosure relates to a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a source region and a drain region in a semiconductor substrate, and a bit line over the source region. The semiconductor device also includes a first epitaxial structure over the drain region, and a capacitor contact over the first epitaxial structure. A bottom surface of the capacitor contact is higher than a bottom surface of the bit line.Type: GrantFiled: November 8, 2019Date of Patent: September 19, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tse-Yao Huang
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Patent number: 11758709Abstract: The present disclosure relates to a method for preparing a semiconductor device. The method includes forming a source region and a drain region in a semiconductor substrate, and forming a bit line over the source region. The method also includes growing a first epitaxial structure over the drain region. A top surface of the first epitaxial structure is higher than a bottom surface of the bit line. The method further includes forming a capacitor contact over the first epitaxial structure.Type: GrantFiled: October 22, 2021Date of Patent: September 12, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tse-Yao Huang
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Patent number: 11677041Abstract: Radiation detecting-structures and fabrications methods thereof are presented. The methods include, for instance: providing a substrate, the substrate including at least one trench extending into the substrate from an upper surface thereof; and epitaxially forming a radiation-responsive semiconductor material layer from one or more sidewalls of the at least one trench of the substrate, the radiation-responsive semiconductor material layer responding to incident radiation by generating charge carriers therein. In one embodiment, the sidewalls of the at least one trench of the substrate include a (111) surface of the substrate, which facilitates epitaxially forming the radiation-responsive semiconductor material layer. In another embodiment, the radiation-responsive semiconductor material layer includes hexagonal boron nitride, and the epitaxially forming includes providing the hexagonal boron nitride with an a-axis aligned parallel to the sidewalls of the trench.Type: GrantFiled: June 22, 2015Date of Patent: June 13, 2023Assignee: Rensselaer Polytechnic InstituteInventors: Rajendra P. Dahal, Ishwara B. Bhat, Yaron Danon, James Jian-Qiang Lu
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Patent number: 11653582Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.Type: GrantFiled: November 8, 2018Date of Patent: May 16, 2023Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SASInventors: Franck Arnaud, David Galpin, Stephane Zoll, Olivier Hinsinger, Laurent Favennec, Jean-Pierre Oddou, Lucile Broussous, Philippe Boivin, Olivier Weber, Philippe Brun, Pierre Morin
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Patent number: 11631753Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.Type: GrantFiled: February 22, 2019Date of Patent: April 18, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Fu Chang, Kuan-Hung Chen, Guang-Yu Lo, Chun-Chia Chen, Chun-Tsen Lu
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Patent number: 11626282Abstract: Provided are a graphene structure and a method of forming the graphene structure. The graphene structure includes a substrate and graphene on a surface of the substrate. Here, a bonding region in which a material of the substrate and carbon of the graphene are covalently bonded is formed between the surface of the substrate and the graphene.Type: GrantFiled: November 8, 2019Date of Patent: April 11, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Eunkyu Lee, Kyung-Eun Byun, Hyunjae Song, Hyeonjin Shin, Changhyun Kim, Keunwook Shin, Changseok Lee, Alum Jung
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Patent number: 11626574Abstract: An organic light-emitting display apparatus includes: a substrate; first and second pixel electrodes on the substrate and spaced from each other; an insulating layer between the first and second pixel electrodes, the insulating layer covering ends of the first and second pixel electrodes, and having a step height difference; an auxiliary electrode on the insulating layer; first and second intermediate layers on the first and second pixel electrodes, the first and second intermediate layers being spaced from each other, and including first and second light-emitting layers, respectively; first and second opposite electrodes on the first and second intermediate layers, the first and second opposite electrodes being spaced from each other, and in contact with the auxiliary electrode; and first and second passivation layers on the first and second opposite electrodes, the first and second passivation layers being spaced from each other, and covering the first and second opposite electrodes, respectively.Type: GrantFiled: April 13, 2020Date of Patent: April 11, 2023Assignee: Samsung Display Co., Ltd.Inventors: Jaesik Kim, Jaeik Kim, Yeonhwa Lee, Joongu Lee, Sehoon Jeong
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Patent number: 11621381Abstract: A micro-LED mounting structure includes a first layer having a conductive pad disposed on a surface thereof, a second layer including a first surface, a second surface opposite the first surface and disposed on the surface of the first layer, and a via-hole extending from the conductive pad of the first layer to the first surface and including a conductive material, and a micro-LED disposed on the first surface of the second layer to be electrically connected with the conductive material included in the via-hole. The via-hole includes a first opening in the first surface of the second layer and in which the conductive material is formed, the conductive material of the first surface provides a conductive area on a portion of the first surface of the second layer, and the conductive area and an area within a specified area of the conductive area define a substantially flat surface.Type: GrantFiled: November 8, 2019Date of Patent: April 4, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Byunghoon Lee, Jamyeong Koo
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Patent number: 11610918Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.Type: GrantFiled: December 5, 2019Date of Patent: March 21, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba
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Patent number: 11532601Abstract: System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.Type: GrantFiled: April 16, 2019Date of Patent: December 20, 2022Assignee: Intel CorporationInventors: Han Wui Then, Robert Chau, Valluri Rao, Niloy Mukherjee, Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Jack Kavalieros
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Patent number: 11480606Abstract: A method for estimating at least one electrical property of a semiconductor device is provided. The method includes forming the semiconductor device and at least one testing unit on a substrate, irradiating the testing unit with at least one electron beam, estimating electrons from the testing unit induced by the electron beam, and estimating the electrical property of the semiconductor device according to intensity of the estimated electrons from the testing unit.Type: GrantFiled: June 14, 2016Date of Patent: October 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Han Wang, Chun-Hsiung Lin