Abstract: A fan-out semiconductor package includes a core member having a through hole, at least one dummy structure disposed in the core member, a semiconductor chip disposed in the through hole and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filling at least a portion of the through hole, and a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad.

Abstract: Aspects of the present disclosure are directed toward designs and methods of manufacturing semiconductor devices, such as semiconductor charge balanced (CB) devices or semiconductor super-junction (SJ) devices. The disclosed designs and methods are useful in the manufacture of CB devices, such as planar CB metal-oxide semiconductor field-effect transistor (MOSFET) devices, as well as other devices.

Abstract: A light emitting device includes a substrate extending in a first direction and a second direction, first through fourth light emitting structures spaced apart from each other in the first and second direction and arranged in a matrix form on the substrate, a plurality of first interconnection layer structures connecting the first light emitting structure to the second light emitting structure, a second interconnection layer structure connecting the second light emitting structure to the third light emitting structure, and a plurality of third interconnection layer structures connecting the third light emitting structure to the fourth light emitting structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first source region, a second source region, a first drain region, and a second drain region. The semiconductor device structure includes a first gate structure over the substrate and between the first source region and the first drain region. The semiconductor device structure includes a second gate structure over the substrate and between the second source region and the second drain region. A first thickness of the first gate structure is greater than a second thickness of the second gate structure. A first gate width of the first gate structure is less than a second gate width of the second gate structure.

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.

Abstract: A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor. The nitrogenous dielectric layer is disposed on the first conductor and the second conductor is disposed on the nitrogenous dielectric layer.

Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region of the first dielectric layer. The gate region includes a region where a gate electrode is to be formed. The mask layer covers the gate region, but does not entirely cover the first dielectric layer. The first dielectric layer not covered by the mask layer is removed such that a source-drain region of the active region is exposed. After that, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. The gate electrode is formed over the gate dielectric layer.

Abstract: A display device includes a substrate, a pixel area, and a plurality of data lines. The substrate includes display and non-display areas. The pixel area is in the display area and includes a first pixel column and a second pixel column. The pixels in the first and second columns emit light of different colors. The data lines are respectively coupled to the first pixel column and the second pixel column. In the non-display area, a data line is coupled to one of the first or second pixel columns corresponding to a color on which influence of a resistance is greater than on another color. The data lines has a line or contact structure with a resistance less than a resistance of a line or contact structure of a remaining data line coupled to a remaining pixel column.

Abstract: A semiconductor device includes a first lower line and a second lower line on a substrate, the first and second lower lines extending in a first direction, being adjacent to each other, and being spaced apart along a second direction, orthogonal the first direction, an airgap between the first and second lower lines and spaced therefrom along the second direction, a first insulating spacer on a side wall of the first lower line facing the second lower line, wherein a distance from the first airgap to the first lower line along the second direction is equal to or greater than an overlay specification of a design rule of the semiconductor device, and a second insulating spacer between the airgap and the second lower line.

Abstract: A semiconductor device includes: a base plate; a semiconductor chip mounted on the base plate; a case surrounding the semiconductor chip on the base plate; an electrode terminal connected to the semiconductor chip; a sealing material covering an upper face of the base plate, the semiconductor chip and a part of the electrode terminal in the case; and a lid fastened to the case above the sealing material, wherein the electrode terminal is not exposed on an upper face of the sealing material, and there is a gap between the upper face of the sealing material and a lower face of the lid.

Abstract: A white light emitting device includes a blue LED chip having a dominant emission wavelength of about 440-465 nm, and a phosphor layer configured to be excited by the dominant emission wavelength of the blue LED chip. The phosphor layer includes a first phosphor having a peak emission wavelength of about 480-519 nm, a second phosphor having a peak emission wavelength of about 520-560 nm, and a third phosphor having a peak emission wavelength of about 620-670 nm. The first phosphor and the second phosphor both have a garnet structure as represented by A3B5O12:Ce, A is selected from the group consisting of Y, Lu, and a combination of thereof, and B is selected from the group consisting of Al, Ga, and a combination of thereof.

Abstract: An active matrix substrate includes, in a peripheral region that is disposed around a display region, a connecting portion formation region in which a plurality of line connecting portions are arranged. Each line connecting portion includes: a lower connecting portion; an organic insulating layer disposed on the lower connecting portion so as to be in contact with the lower connecting portion, the organic insulating layer having at least one aperture through which a part of the lower connecting portion is exposed; and an upper connecting portion disposed on the organic insulating layer and in the at least one aperture, the upper connecting portion being directly in contact with the part of the lower connecting portion within the at least one aperture. The organic insulating layer extends into an adjoining region that adjoins the connecting portion formation region.

Abstract: An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.

Abstract: A method for forming a semiconductor device includes recessing a gate conductor in a gate structure to form a first divot, forming a gate cap in the first divot and recessing a dielectric fill that encapsulates the gate structures to a position below a top of the gate cap. An extension layer is deposited over the dielectric fill and the top of the gate cap and is planarized to the top of the gate cap. The extension layer is expanded to form a profile growth layer that is thicker than the extension layer and creates a second divot over the gate cap. A top cap is formed in the second divot to provide a cap with a thickness of the gate cap and the top cap.

Abstract: The disclosure relates to a semiconductor device including a first planar field effect transistor cell and a second planar field effect transistor cell. The first planar field effect transistor cell and the second planar field effect transistor cell are electrically connected in parallel and each include a drain extension region between a channel region and a drain terminal at a first surface of a semiconductor body. A gate electrode of the first field effect transistor cell is electrically connected to a source terminal, and a gate electrode of the second field effect transistor cell is connected to a gate terminal that is electrically isolated from the source terminal.

Abstract: A semiconductor device includes a substrate with a buffer region between first and second regions, the first region being a SRAM cell region, and the second region being a peripheral circuit region, first gate structures in a first direction on the first region and being spaced apart from each other in a second direction, second gate structures in the first direction on the second region and being spaced apart from each other in the second direction, the first and second gate structures being aligned with each other, a first insulating structure in the second direction on the buffer region between the first and the second regions along an entire length of each of the first and second regions in the second direction, and a second insulating structure on the first region and in contact with a part of the plurality of first gate structures.

Abstract: A fin field effect transistor (FinFET) ESD device is disclosed. The device may include: a substrate; a silicon-controlled rectifier (SCR) over the substrate, the SCR including: a p-well region over the substrate; an n-well region laterally abutting the p-well region over the substrate; a first P+ doped region over the p-well region; a first N+ doped region over the p-well region; and a second N+ doped region over the p-well region; and a Schottky diode electrically coupled to the n-well region, wherein the Schottky diode spans the n-well region and the p-well region, and wherein the Schottky diode controls electrostatic discharge (ESD) between the second N+ doped region and the n-well region.

Abstract: A packaged semiconductor device includes a metal substrate having a first and second through-hole aperture having an outer ring, and metal pads around the apertures on dielectric pads. A first and second semiconductor die have a back side metal (BSM) layer on its bottom side are mounted top side up on a top portion of the apertures. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the apertures to provide a die attachment for the first and the second semiconductor die that fills a bottom portion of the apertures. Leads contact the metal pads, wherein the leads include a distal portion that extends beyond the metal substrate. Bondwires are between the metal pads and bond pads on the first and second semiconductor die, and a mold compound provides encapsulation for the packaged semiconductor device.

Abstract: A display device includes a display panel including a flexible region and a low flexibility region, wherein the flexible region may include a first transistor including a first semiconductor layer and a first gate electrode, a first conductor connected to the first semiconductor layer, and a first interlayer insulating layer between the first transistor and the first conductor. The low flexibility region may include a second transistor including a second semiconductor layer and a second gate electrode, a second conductor connected to the second semiconductor layer, and a second interlayer insulating layer between the second transistor and the second conductor. The first interlayer insulating layer may include an organic insulating material, the second interlayer insulating layer includes an inorganic insulating material, and a ratio of channel width to channel length of the first transistor may be different from that of the second transistor.

Abstract: An electronic device includes a spreading layer and a first contact layer formed over and contacting the spreading layer. The first contact layer is formed from a thermally conductive crystalline material having a thermal conductivity greater than or equal to that of an active layer material. An active layer includes one or more III-nitride layers. A second contact layer is formed over the active layer, wherein the active layer is disposed vertically between the first and second contact layers to form a vertical thin film stack.