Patents Examined by Kenneth Lo
  • Patent number: 8572329
    Abstract: A data processing system is provided with a programmable memory protection unit 10 defining a plurality of programmable memory regions 2, 4, 6, 8 each with associated programmable memory attributes. A default memory protection unit 22 is provided and defines a plurality of default memory regions a, b, c, d, e each with associated default memory attributes. If a miss occurs in the programmable memory protection unit 10, and the memory access is a privileged level memory access, then the default memory protection unit 22 will return default memory attributes for that memory request.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: October 29, 2013
    Assignee: ARM Limited
    Inventors: Simon Axford, Simon John Craske, Paul Kimelman
  • Patent number: 8566527
    Abstract: A system and a method are described, whereby a data cache enables the realization of an efficient design of a usage analyzer for monitoring subscriber access to a communications network. By exploiting the speed advantages of cache memory, as well as adopting innovative data loading and retrieval choices, significant performance improvements in the time required to access the necessary data records can be realized.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: October 22, 2013
    Assignee: Bridgewater Systems Corp.
    Inventors: Timothy James Reidel, Li Zou
  • Patent number: 8566516
    Abstract: One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: October 22, 2013
    Assignee: Google Inc.
    Inventors: Keith R. Schakel, Suresh Natarajan Rajan, Michael John Sebastian Smith, David T. Wang
  • Patent number: 8549253
    Abstract: A system integrates an intelligent storage switch with a flexible virtualization system to enable the intelligent storage switch to provide efficient service of file and block protocol data access requests for information stored on the system. A storage operating system executing on a storage system coupled to the switch implements the virtualization system to provide a unified view of storage to clients by logically organizing the information as named files, directories and logical unit numbers. The virtualization system may be embodied as a file system having a write allocator configured to provide a flexible block numbering policy to the storage switch that addresses volume management capabilities, such as storage virtualization.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: October 1, 2013
    Assignee: NetApp, Inc.
    Inventors: Vijayan Rajan, Brian Pawlowski, Jeffrey S. Kimmel, Gary Ross
  • Patent number: 8539156
    Abstract: When a command to restore a logical unit is issued after a command to delete the logical unit, the logical unit is restored easily. When a controller receives an LU deletion command from a management terminal and if the relevant LU is a normal LU, it retains information about the deletion target LU, from among information in an LU management table, as reset information; and if the relevant LU is a virtual LU, the controller retains information about the deletion target LU, from among information in a virtual address table, as the reset information. If the controller receives an LU restoration command to restore the deletion target LU as an access target LU, from the management terminal, it restores the retained reset information as setting information corresponding to the access target LU and manages the restored setting information by using the LU management table or the virtual address table, thereby processing an access request from a host computer.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: September 17, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Kamon, Yoshihiro Uchiyama
  • Patent number: 8521951
    Abstract: Embodiments of the present disclosure provide methods, apparatuses, and systems including a memory device including content addressable memory configured to store an address associated with one or more memory cells while an access operation is performed on the one or more memory cells. Other embodiments may be described.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: August 27, 2013
    Assignee: S. Aqua Semiconductor LLC
    Inventor: G. R. Mohan Rao
  • Patent number: 8495336
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: July 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
  • Patent number: 8495321
    Abstract: A mechanism is provided for firehose dumping modified data in a static random access memory of a hard disk drive to non-volatile memory of the hard disk drive during a power event. Responsive an indication of a power event in the hard disk drive, hard disk drive command processing is suspended. A token is set in the non-volatile storage indicating that flash memory in the non-volatile memory contains modified data. A portion of a static random access memory cache table containing information on the modified data in the static random access memory is copied to the flash memory. The modified data from the static random access memory is then copied to the flash memory. Responsive to a determination that the power event that initiated the copy of the modified data in the static random access memory to the flash memory is still present, the hard disk drive is shut down.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michael L. Harper, Craig A. Klein, Gregg S. Lucas, Mary A. J. Marquez, Robert E. Medlin
  • Patent number: 8495278
    Abstract: A controller includes an instruction table memory, a program counter, a first decoder, and a first executing unit. The instruction table memory stores an instruction code obtained by coding a sequence to access a nonvolatile semiconductor memory. A read address in the instruction table memory is set to the program counter. The first decoder decodes the instruction code read from the instruction table memory to output a first decode signal. The first executing unit executes access to the nonvolatile semiconductor memory on the basis of the first decode signal output from the first decoder.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: July 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tarou Iwashiro, Takahide Nishiyama, Seiichi Tomita
  • Patent number: 8473683
    Abstract: A parallel computing system processes at least one store instruction. A first processor core issues a store instruction. A first queue, associated with the first processor core, stores the store instruction. A second queue, associated with a first local cache memory device of the first processor core, stores the store instruction. The first processor core updates first data in the first local cache memory device according to the store instruction. The third queue, associated with at least one shared cache memory device, stores the store instruction. The first processor core invalidates second data, associated with the store instruction, in the at least one shared cache memory. The first processor core invalidates third data, associated with the store instruction, in other local cache memory devices of other processor cores. The first processor core flushing only the first queue.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: Alan Gara, Martin Ohmacht
  • Patent number: 8458432
    Abstract: Provided is a computer system, in which a storage system includes a first control module for logically dividing first resources of the storage system and operating them as independent virtual storage systems. A computer includes a second control module for logically dividing second resources of the computer and operating them as independent virtual machines. The computer system holds first information indicating a correlation among the virtual machine, the virtual storage system, and the first resources. The first control module specifies the first resource allocated to the virtual storage system whose power is cut based on the first information, and powers off the specified first resource. Thus, system power consumption can be reduced by managing power of the storage system shared by a plurality of virtual machines in a virtualization environment.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: June 4, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Akiyoshi Hashimoto, Shuji Nakamura, Kazuhisa Fujimoto
  • Patent number: 8443148
    Abstract: Methods and apparatus relating to system-wide quiescence and per-thread transaction fence in a distributed caching agent are described. Some embodiments utilize messages, counters, and/or state machines that support system-wide quiescence and per-thread transaction fence flows. Other embodiments are also disclosed.
    Type: Grant
    Filed: December 26, 2010
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: James R. Vash, Bongjin Jung, Rishan Tan
  • Patent number: 8407407
    Abstract: A drive control module of a solid-state drive (SSD) includes a first module that receives host commands from one of a host command buffer and a drive interface of the SSD, converts the host commands to stage commands, and determines whether to store the stage commands in a stage slot of a staging memory or leave the stage slot empty. A second module transfers data between a buffer and a flash memory based on the stage commands. The flash memory comprises flash arrays. A third module detects a first empty stage of one of the flash arrays and based on an empty stage timer value triggers at least one of an end of the first empty stage, a start of an at least partially full stage of the one of the flash arrays, or a start of a second empty stage of the one of the flash arrays.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: March 26, 2013
    Assignee: Marvell International Ltd.
    Inventors: Jason Adler, Lau Nguyen, Perry Neos
  • Patent number: 8402250
    Abstract: A system and method are provided for deduplication (dedup) of data file information in a network of distributed data filers. A host, including a metadata service (MDS) and a data node (DN), receives a block count and hash group calculations for a file from a network-connected client device. The MDS creates a file map with target addresses, and compares the calculated hash group to hash groups associated with stored blocks of data in a global dedup hash table. If a match is found, the MDS directs the client device not to send the block of data associated with matching hash group, and reallocates the address of the block of data from the target address.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: March 19, 2013
    Assignee: Applied Micro Circuits Corporation
    Inventor: Loic Juillard
  • Patent number: 8402210
    Abstract: Provided is a disk array system which is connected to a computer and which data is transmitted by the computer, including: a plurality of disk drives for storing user data transmitted by the computer; a cache memory for temporarily storing data sent/received among the computer and the plurality of disk drives; and a control unit for controlling input/output of the data to/from the cache memory, in which the control unit stores user data identification information that is capable of judging whether the user data is stored in a sector of the disk drive. The disk array system according to this invention allows the identification of user data of a disk drive.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: March 19, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Akihiro Mannen, Yoichi Mizuno, Masahiro Arai
  • Patent number: 8386720
    Abstract: A method of allowing exclusive access to shared data by a computing device and a computer readable article embodying instructions for executing the method. The method includes: reading from a storage unit into a memory a program including a code for execution in a critical section and an instruction to write a value into or read a value from a shared data area in the memory; acquiring a lock on the critical section before start of a first instruction in the critical section; writing a value into a thread-local area in the memory in response to an instruction to write the value into the shared data area; writing into the shared data area the value written into the thread-local area upon completion of a final instruction in the critical section; and releasing the lock on the critical section, thereby allowing exclusive access to shared data.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: February 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Tatsushi Inagaki, Takuya Nakaike, Takeshi Ogasawara, Toshio Suganuma
  • Patent number: 8386725
    Abstract: The present invention aims to provide a USB host controller capable of reducing time for a data transfer between storage devices. A USB host controller according to the present invention includes a buffer memory for USB pipe having a first buffer memory region and a second buffer memory region, and a buffer memory controller configured to control a data transfer between the buffer memory for USB pipe and each of first and second devices. The buffer memory controller stores data from the first device in the first buffer memory region, swaps address information corresponding to the first buffer memory region and address information corresponding to the second buffer memory region, and transfers data stored in the first buffer memory region to the second device, on the basis of the address information corresponding to the first buffer memory region after the swapping.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: February 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Kunihiro Kondo
  • Patent number: 8307173
    Abstract: A technique for reducing reader overhead when referencing a shared data element while facilitating realtime-safe detection of a grace period for deferring destruction of the shared data element. The grace period is determined by a condition in which all readers that are capable of referencing the shared data element have reached a quiescent state subsequent to a request for a quiescent state. Common case local quiescent state tracking may be performed using only local per-reader state information for all readers that have not blocked while in a read-side critical section in which the data element is referenced. Uncommon case non-local quiescent state tracking may be performed using non-local multi-reader state information for all readers that have blocked while in their read-side critical section. The common case local quiescent state tracking requires less processing overhead than the uncommon case non-local quiescent state tracking.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: November 6, 2012
    Assignee: International Business Machines Corporation
    Inventor: Paul E. McKenney
  • Patent number: 8307177
    Abstract: Described in detail herein is a method of copying data of one or more virtual machines being hosted by one or more non-virtual machines. The method includes receiving an indication that specifies how to perform a copy of data of one or more virtual machines hosted by one or more virtual machine hosts. The method may include determining whether the one or more virtual machines are managed by a virtual machine manager that manages or facilitates management of the virtual machines. If so, the virtual machine manager is dynamically queried to automatically determine the virtual machines that it manages or that it facilitates management of. If not, a virtual machine host is dynamically queried to automatically determine the virtual machines that it hosts. The data of each virtual machine is then copied according to the specifications of the received indication.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: November 6, 2012
    Assignee: CommVault Systems, Inc.
    Inventors: Anand Prahlad, Rahul S. Pawar, Prakash Varadharajan, Pavan Kumar Reddy Bedadala
  • Patent number: 8285969
    Abstract: Disclosed is an apparatus to reduce broadcasts in multiprocessors including a plurality of processors; a plurality of memory caches associated with the processors; a plurality of translation lookaside buffers (TLBs) associated with the processors; and a physical memory shared with the processors memory caches and TLBs; wherein each TLB includes a plurality of entries for translation of a page of addresses from virtual memory to physical memory, each TLB entry having page characterization information indicating whether the page is private to one processor or shared with more than one processor. Also disclosed is a computer program product and method to reduce broadcasts in multiprocessors.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: October 9, 2012
    Assignee: International Business Machines Corporation
    Inventors: Khubaib Khubaib, Moinuddin Khalil Ahmed Qureshi, Vijayalakshmi Srinivasan