Abstract: An apparatus for zero voltage switching includes a ZVS assist circuit connected between a switching node and a negative connection of a converter. The switching node is located between first and second switches of a switching leg of the converter. The converter is fed by a constant current source and feeds a constant current load. The ZVS assist circuit includes a ZVS inductance, a first ZVS switch that allows current through the ZVS inductance to change a voltage of the switching node to a condition for zero voltage switching of the first switch of the switching leg, and a second ZVS switch that allows current through the ZVS inductance to change the voltage of the switching node to a condition for zero voltage switching of the second switch of the switching leg. Current through the first ZVS switch is opposite current through the second ZVS switch.

Abstract: A flyback converter communication channel is provided that comprises a pair of capacitors. A transmitter on a first side of a transformer for the flyback converter transmits a transmitter signal over a first one of the capacitors. The transmitter also transmits a complement of the transmitter signal over a second one of the capacitors. A receiver on a second side of the transformer controls a switch transistor responsive to a high-pass-filtered difference of the received signals from the pair of capacitors.

Abstract: A converter control system includes first and second step-up converters and first and second electronic control units. The first and second electronic control units are respectively configured to generate first and second PWM driving signals for the first and second step-up converters. The second electronic control unit is configured to determine whether a first carrier and a second carrier are synchronous with each other based on the first PWM driving signal, a first duty ratio, and the second carrier. The second electronic control unit is configured to, when the second electronic control unit determines that the first carrier and the second carrier are not synchronous with each other, shut down the second step-up converter and then restart generation of the second PWM driving signal with the second carrier synchronous with the first carrier with the use of the first PWM driving signal and the first duty ratio.

Abstract: A power compensator for compensating voltage at a location along a power transmission line, the compensator having a controller for controlling a voltage generated across the compensator, wherein the voltage is controlled to maintain a power transmission line voltage at a value dependent on the power transmission line location.

Abstract: Adaptive slope compensation for current mode control in a switch mode power supply converter is computed for every switching cycle based upon the input voltage and duty-cycle whereby the quality factor is maintained at a constant value. A digital signal processing (DSP) capable microcontroller comprises a voltage loop compensator and generates a desired current reference for every switching cycle. Slope calculations are adapted for switching frequency, inductance value, current circuit gain, etc. The slope calculation result is applied to a pulse-digital-modulation (PDM) digital-to-analog converter (DAC) capable of changing its output levels at a very fast rate compared to the power supply switching frequency whereby the required current slope is provided within the switching period. Actual inductor current may be used to compare against the slope reference, thereby taking care of changes in the inductance values under load. The slope levels are automatically changed when the switching frequency is changed.

Abstract: A voltage regulator includes a voltage converter is configured to generate an output power supply voltage based on an input power supply voltage and an input reference voltage and provide the output power supply voltage to an external functional circuit, the voltage converter including an output terminal configured to output the output power supply voltage; and a sinker connected to the output terminal, the sinker configured to generate a sink current in response to a sink enable signal while the external functional circuit is not driven and configured to block generation of the sink current in response to an operating enable signal while the external functional circuit is driven, wherein the sink current corresponds to a load current that is to be consumed while the external functional circuit is driven.

Abstract: Rectifier circuit. At least some of the example embodiments are circuits including: an anode terminal; a cathode terminal; a field effect transistor (FET) defining a drain, source, and gate, the source coupled to the anode terminal, and the drain coupled to the cathode terminal; a diode having anode and cathode, the anode coupled to the cathode terminal; a bootstrap capacitor coupled between the cathode of the diode and the anode terminal; a FET controller coupled to the gate of the FET and a node between the diode and bootstrap capacitor; the FET controller configured to make the FET conductive as the circuit becomes forward biased, and the FET controller configured to make the FET non-conductive during periods of time when the circuit is reverse biased.

Abstract: Disclosed are a new phase shift full bridge (PSFB) converter using a clamp circuit connected to a center-tapped clamp circuit and an operating method thereof. The new PSFB converter using a clamp circuit connected to a center-tapped clamp circuit includes a primary-side circuit including a plurality of inductors connected to one end between a first switch and a second switch which are connected in series and to one end between a third switch and a fourth switch which are connected in series and a secondary-side circuit using a voltage applied by the primary-side circuit and including a clamping circuit configured with a first rectifier diode, a second rectifier diode, a third rectifier diode, a fourth rectifier diode, a first clamping diode, a second clamping diode and a capacitor in a center-tapped clamp circuit.

Abstract: A method of operating a multilevel power converter includes using, through a processing device, a model of an electrical circuit that includes a plurality of switching devices, a plurality of flying capacitors, and an AC terminal. The method also includes regulating a voltage level of the AC terminal through selecting, at least partially based on the model, a possible charging state of the electrical circuit. Each possible switching state has a voltage level that at least partially corresponds to a commanded voltage level for the AC terminal. The method further includes selecting, at least partially based on the model of the electrical circuit and at least partially based on the selected possible switching state, a charging state from a plurality of possible charging states. The method also includes setting the switching state of the electrical circuit at least partially based on the selected charging state of the electrical circuit.

Abstract: Systems and methods to improve operation of a modular multilevel converter. Some embodiments include a first upper arm with a first active power link module, which facilitates producing a first portion of a first alternating current electrical power at a base frequency and injecting a first even-order current harmonic of the base frequency in the first upper arm, and a first lower arm with a second active power link module, which facilitates producing a second portion of the first alternating current, in which the first portion of the first alternating current and the second portion of the alternating current are combined to facilitate outputting the first alternating current electrical power at a first alternating current terminal, and injecting the first even-order current harmonic in the first lower arm, in which magnitude of the first even-order current harmonic is zero at the first alternating current terminal.

Abstract: A dual rail power supply system and a method for providing a first voltage and a second voltage to a load are presented. The power supply system draws a load current from the dual rail power supply system. The system has a first voltage rail for coupling to a first terminal of the load, a second voltage rail for coupling to a second terminal of the load, a first power converter to provide the first voltage at the first voltage rail, a second power converter to provide the second voltage at the second voltage rail, a third power converter comprising a first output coupled to the first voltage rail and a second output coupled to the second voltage rail. The third power converter generates a slave current and provides the slave current to the load such that the load current comprises the slave current, during a first mode.

Abstract: An active clamp circuit includes an active clamp capacitor coupled in series with an active clamp switch and an active clamp controller circuit to receive an active clamp switch current that passes through the active clamp switch and to control the active clamp switch based on the received active clamp switch current. The active clamp controller circuit is configured to enable the active clamp switch based on a first amplitude comparison, the first amplitude comparison being based on the active clamp switch current. The active clamp controller circuit is configured to disable the active clamp switch based on a second amplitude comparison and a third amplitude comparison, the second amplitude comparison and the third amplitude comparison being based on the active clamp switch current.

Abstract: A method and arrangement for controlling semiconductor power switches, e.g. IGBTs, in parallel connected power devices, e.g. in frequency converters, wherein the semiconductor power switches connect either the positive or the negative pole of the intermediate DC-voltage of the power device to an output phase of the power device. In the method the voltages of those output phases which are connected in parallel are measured, the timing differences of the output voltage state changes are calculated on the basis of the output voltage measurement results, and the control signals of the semiconductor power switches are advanced or delayed such that the output voltage state changes in the phases which are connected together via output impedances occur at desired time instants.

Abstract: In accordance with an embodiment, a proportional to absolute temperature (PTAT) circuit includes a first bipolar transistor having a collector coupled to a common node; a second bipolar transistor having a collector coupled to the common node; a MOSFET having a load path coupled between a base of the first bipolar transistor and a base of the second bipolar transistor; and an amplifier having a first input coupled to an emitter of the first bipolar transistor, a second input coupled to an emitter of the second bipolar transistor and an output coupled to a gate of the MOSFET.

Abstract: A control circuit controls a switching circuit of a resonant converter where the switching circuit includes first and second power switches. A first on time of the first power switch and a second on time of the second power switch are controlled to generate a square wave signal to drive the resonant circuit. The control circuit controls the first on time based on a zero current detection time indicating detection of a zero current crossing of a resonant current generated in the resonant circuit in response to the square wave signal and on a time shift delay time based on an output voltage of the resonant converter. The second on time of the second power switch control is based on the zero current detection time detected for the first power switch and on the time shift delay time.

Abstract: A multi-level voltage converter having a first switching circuit including a flying capacitor coupled in parallel with first switches coupled in series, the first switches configured to be driven by a first duty command having a first duty cycle; a second switching circuit including the flying and second switches coupled in series between input voltage terminals of an input voltage, the second switches configured to be driven by a second duty command having a second duty cycle; and a control circuit configured to balance a voltage of the flying capacitor by controlling an interleaved constant frequency modulator to generate the first and second duty cycle commands such that the first and second duty cycles are the same.

Abstract: An apparatus comprises an Ethernet port including high-side transformers and low-side transformers. High-side current paths supply high-side currents form a high voltage rail to high-side center taps of the high-side transformers. Low-side current paths supply or do not supply low-side currents from a low voltage rail to low-side center taps of the low-side transformers, and convert the low-side currents to sense voltages. A controller configures the low-side current paths to either supply or not supply the low-side currents to the low-side center taps when none of the sense voltages exceed a voltage threshold representative of an overcurrent threshold or when at least one of the sense voltages exceeds the voltage threshold, respectively. A current monitor injects additional current into the low-side current paths only when at least one of the high-side currents exceeds the overcurrent threshold.

Abstract: A gate-drive system according to the present invention which transmits a drive signal to a semiconductor switching device, includes: an inverter circuit to supply high-frequency power including a fundamental wave component and plural harmonic components each having different frequencies; a power transmission circuit which is connected to the inverter circuit and transmits the high-frequency power outputted from the inverter circuit; power receiving circuits to individually receive the fundamental wave component and plural harmonic components of the high-frequency power transmitted from the power transmission circuit; and a control circuit to generate the drive signal for the semiconductor switching device on the basis of the plural harmonic components of the high-frequency power received by the power receiving circuits.

Abstract: A power management module comprises one or more power converter chips that are mounted on a power management package substrate. First and second electrical contacts are disposed on opposing first and second sides of the power management package substrate. The power management module can be mounted on a processor module to supply power to one or more processor chips in the processor module. In one example, the processor chip(s) are mounted on a first side of a processor package substrate and the power management module is mounted on an opposing second side of the processor package substrate. The power management module and the processor module can be centered and aligned with respect to each other or they can be offset laterally from each other. In another embodiment, the processor chip(s) are embedded in the processor package substrate.

Abstract: A voltage regulator includes power stages and a controller. The power stages are configured to provide power to a load in response to a pulse-width modulated (PWM) signal and to provide a body braking to the load in response to a body braking signal. The body braking is provided via a body diode of the power stage. The controller is configured to provide the PWM signals to a first power stage and a second power stage based upon a power demand of the load, to provide body braking signals to the first power stage and the second power stage in response to an over-voltage condition on the load, and to suspend the first body braking signal to the first power stage and maintain the second body braking signal to the second power stage, in response to an over-temperature condition on the first power stage.