Patents Examined by Kevin Parendo
  • Patent number: 10338438
    Abstract: The embodiments of the invention disclose an array substrate, a manufacturing method thereof and a display device. Due to the fact that the surfaces of a source electrode, a drain electrode and a data line which are arranged on the same layer are provided with an oxide film which is formed after annealing treatment is conducted on the source electrode, the drain electrode and the data line, in the process that the pattern of a pixel electrode is formed on the source electrode, the drain electrode and the data line by the adoption of a composition technology, the oxide film can protect the source electrode and the data line under the oxide film from being corroded by an etching agent when the pattern of the pixel electrode is formed by etching, and the display quality of a display panel will not be affected.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: July 2, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Seungjin Choi, Heecheol Kim, Youngsuk Song, Seongyeol Yoo
  • Patent number: 10325853
    Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Wei Lin, Ming-Da Cheng
  • Patent number: 10290512
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 14, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 10290751
    Abstract: A radiation detector (10) which has a multilayer structure that includes: a first electrode (34); a second electrode (49) that is disposed so as to face the first electrode; a selenium layer (48) that is disposed between the first electrode and the second electrode and contains amorphous selenium; a first blocking organic layer (38) that is adjacent to the selenium layer, between the first electrode and the selenium layer, and that contains a hole transport material having an electron affinity of 3.7 eV or less; and a second blocking organic layer (37) that is adjacent to the selenium layer, between the second electrode and the selenium layer, and that contains an electron transport material having an ionization potential of 5.9 eV or more. This radiation detector (10) has low dark current, excellent durability, and less afterimages.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: May 14, 2019
    Assignee: FUJIFILM CORPORATION
    Inventors: Seiji Yamashita, Toshihiro Ise
  • Patent number: 10256328
    Abstract: A method for forming a semiconductor device includes forming first fins from a first semiconductor material and second fins from a second semiconductor material and encapsulating the first fins and the second fins with a protective dielectric. Semiconductor material between the first fins and the second fins is etched to form trenches. A dielectric fill is employed to fill up the trenches, between the first fins and between the second fins. The first semiconductor material below the first fins and the second semiconductor material below the second fins are oxidized with the first and second fins being protected by the protective dielectric. Fins in an intermediary region between the first fins and the second fins are oxidized to form dummy fins in the intermediary region to maintain a substantially same topology across the device.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10256275
    Abstract: An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the source/drain regions of one of the select transistors. The local second vertical line is in conductive connection with the other source/drain region of the one select transistor. Individual memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects and implementations, including methods, are disclosed.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: April 9, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Zengtao T. Liu
  • Patent number: 10224464
    Abstract: A package for mounting a light emitting element includes: a first lead electrode having, in a plan view, a first region, a second region surrounding a periphery of the first region having a width of 110 ?m or more and a thickness greater than that of the first region, and a third region partially surrounding a periphery of the second region and having a thickness smaller than that of the second region; a second lead electrode spaced apart from the first lead electrode; and a resin molded body fixing a portion of each of the first and second lead electrodes. A portion of each of the first and second lead electrodes and a portion of the resin molded body exposed therebetween form a bottom surface of a recess.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: March 5, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Koji Abe, Yuki Shiota
  • Patent number: 10192967
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate oxide film, and a gate electrode. A trench is provided in the main surface to have a side surface and a bottom portion. A contact point between a first side surface portion and a second side surface portion is located in a third impurity region. An angle formed by the first side surface portion and a straight line extending through the contact point and parallel to the main surface is smaller than an angle formed by the second side surface portion and a boundary surface between a first impurity region and a second impurity region. A thickness of a portion of the gate oxide film on the contact point between the main surface and the first side surface portion is larger than a thickness of a portion of the gate oxide film on the second impurity region.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: January 29, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yu Saitoh, Tomoaki Hatayama, Takeyoshi Masuda
  • Patent number: 10177098
    Abstract: A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: January 8, 2019
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Karine Saxod, Marika Sorrieul
  • Patent number: 10163949
    Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Yu Lai, Min-Ying Tsai, Yeur-Luen Tu, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Patent number: 10164146
    Abstract: A light emitting device includes a p-side heterostructure having a short period superlattice (SPSL) formed of alternating layers of AlxhighGa1-xhighN doped with a p-type dopant and AlxlowGa1-xlowN doped with the p-type dopant, where xlow?xhigh?0.9. Each layer of the SPSL has a thickness of less than or equal to about six bi-layers of AlGaN.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: December 25, 2018
    Assignee: Palo Alto Research Center Incorporated
    Inventors: John E. Northrup, Bowen Cheng, Christopher L. Chua, Thomas Wunderer, Noble M. Johnson, Zhihong Yang
  • Patent number: 10134904
    Abstract: Provided is a flexible device with fewer defects caused by a crack or a flexible device having high productivity. A semiconductor device including: a display portion over a flexible substrate, including a transistor and a display element; a semiconductor layer surrounding the display portion; and an insulating layer over the transistor and the semiconductor layer. When seen in a direction perpendicular to a surface of the flexible substrate, an end portion of the substrate is substantially aligned with an end portion of the semiconductor layer, and an end portion of the insulating layer is positioned over the semiconductor layer.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: November 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Adachi, Kayo Kumakura
  • Patent number: 10128184
    Abstract: An antifuse structure includes a first electrode layer, an inter-metal dielectric layer over the first electrode layer, and a via in the inter-metal dielectric layer. The via penetrates through the inter-metal dielectric layer exposing a portion of the first electrode layer. An antifuse layer is deposited in the via and over the portion of the first electrode layer. A second electrode is disposed in the via and over the antifuse layer. An interconnect layer may be deposited over the inter-metal dielectric layer and in electrical contact with the second electrode in the via.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: November 13, 2018
    Assignee: Zhuhai Chuangfeixin Technology Co., Ltd.
    Inventors: Li Li, Zhigang Wang
  • Patent number: 10074777
    Abstract: A light emitting diode (LED) structure including a stacked semiconductor layer, a contact layer and a dielectric reflective layer is provided. The stacked semiconductor layer includes a first type doped layer, a second type doped layer and an active layer disposed between the first type doped layer and the second type doped layer, wherein the first type doped layer, the active layer and the second type doped layer are penetrated by a plurality of recesses. The contact layer is disposed on the second type doped layer. The dielectric reflective layer is disposed on the contact layer and extended into the recesses to connect the contact layer and the first type doped layer with a coverage rate equal to or less than 60% from a top view of the LED structure.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: September 11, 2018
    Assignee: Epistar Corporation
    Inventors: Cheng-Kuang Yang, Hui-Ching Feng, Chien-Pin Hsu, Kuo-Hui Yu, Shyi-Ming Pan
  • Patent number: 10068865
    Abstract: A combing bump structure includes a semiconductor substrate, a pad, a conductive layer, a solder bump and at least two metal side walls The pad is disposed on the semiconductor substrate. The conductive layer is disposed on the pad. The solder bump is disposed on the conductive layer. The at least two metal side walls are disposed along opposing outer side walls of the solder bump respectively.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: September 4, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 10056376
    Abstract: A semiconductor device includes a semiconductor substrate and a fin positioned above the semiconductor substrate, wherein the fin includes a semiconductor material. Additionally, a ferroelectric high-k spacer covers sidewall surfaces of the fin and a non-ferroelectric high-k material layer covers the ferroelectric high-k spacer and the fin, wherein a portion of the non-ferroelectric high-k material layer is positioned on and in direct contact with the semiconductor material at the upper surface of the fin.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen, Jan Hoentschel
  • Patent number: 10050104
    Abstract: A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chewn-Pu Jou, Chih-Hsin Ko, Po-Wen Chiu, Chao-Ching Cheng, Chun-Chieh Lu, Chi-Feng Huang, Huan-Neng Chen, Fu-Lung Hsueh, Clement Hsingjen Wann
  • Patent number: 9978740
    Abstract: A unidirectional transient voltage suppressor (TVS) device is formed with first and second NPN transistors that are connected in parallel to each other. Each NPN transistor includes a collector region, an emitter. The first and second NPN structures are formed on a common substrate. The first NPN transistor has a floating base and the second NPN transistor has a base shorted to an emitter.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: May 22, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla
  • Patent number: 9978604
    Abstract: A method of forming a semiconductor device includes forming a gate stack over a first portion of a source and a first portion of a drain. The method includes depositing a first cap layer comprising silicon over a second portion of the source and depositing a second cap layer comprising silicon over a second portion of the drain. The method includes depositing a metal layer over the gate stack, the first cap layer and the second cap layer. The method includes annealing the semiconductor device until all of the silicon in the first and second cap layers reacts with metal from the metal layer, wherein the annealing causes metal from the metal layer to react with silicon in the first cap layer, the second cap layer, the source, and the drain. Annealing the semiconductor device includes forming a salicide layer having a germanium concentration less than 3% by weight.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mei-Hsuan Lin, Chih-Hsun Lin, Ching-Hua Chu, Ling-Sung Wang
  • Patent number: 9972759
    Abstract: The invention relates to a device (1), comprising at least one optoelectronic semiconductor component (2) and a substrate (5), on which the semiconductor component is arranged, wherein an insulating layer (4) is adjacent to a lateral surface (25) that bounds the semiconductor component; a contact track (6) is arranged on a radiation passage surface of the semiconductor component and is connected to an electrically conductive manner to the semiconductor component; the contact track extends beyond the lateral surface of the semiconductor component and is arranged on the insulating layer; and the contact track is relieved with respect to a thermomechanical load occurring perpendicularly to the lateral surface.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: May 15, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Walter Wegleiter, Paola Altieri-Weimar, Juergen Moosburger, Stefan Stegmeier, Karl Weidner