Patents Examined by Kevin Parendo
  • Patent number: 11450789
    Abstract: It is an object of the present invention to improve light source efficiency of “a light-emitting device capable of realizing a natural, vivid, highly visible and comfortable appearance of colors or an appearance of objects” already arrived at by adopting a spectral power distribution having a shape completely different from the shape of conventionally known spectral power distributions while maintaining favorable color appearance characteristics.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: September 20, 2022
    Assignee: CITIZEN ELECTRONICS CO., LTD.
    Inventor: Hideyoshi Horie
  • Patent number: 11444255
    Abstract: A flexible display device is manufactured with high yield. A display device having high resistance to repeated bending is provided. The display device is manufactured by forming a separation layer over a support substrate; forming, over the separation layer, an inorganic insulating layer including a first portion and a second portion; forming a display element over the inorganic insulating layer to be overlapped with the first portion; forming a connection electrode over the inorganic insulating layer to be overlapped with the second portion; sealing the display element; separating the support substrate and the inorganic insulating layer using the separation layer; attaching a substrate to the inorganic insulating layer to be overlapped with the first portion; and etching the second portion using the substrate as a mask to expose the connection electrode.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: September 13, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takaaki Nagata, Tatsuya Sakuishi, Kohei Yokoyama, Yasuhiro Jinbo, Taisuke Kamada, Akihiro Chida
  • Patent number: 11437464
    Abstract: Embodiments of a three-dimensional capacitor for a memory device and fabrication methods are disclosed. The method includes forming, on a first side of a first substrate, a peripheral circuitry having a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode. The method also includes forming, on a second substrate, a memory array having a plurality of memory cells and a second interconnect layer, and bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array. The method further includes forming, on a second side of the first substrate, one or more trenches inside the deep well, disposing a capacitor dielectric layer on sidewalls of the one or more trenches, and forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: September 6, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Liang Chen, Cheng Gan, Wei Liu, Shunfu Chen
  • Patent number: 11404564
    Abstract: A semiconductor device including a transistor section and a diode section, the semiconductor device having: a temperature sensing section; a neighboring transistor section adjacent to the temperature sensing section; a neighboring diode section adjacent to the temperature sensing section; and a first non-neighboring diode section that is not adjacent to the temperature sensing section, wherein the first non-neighboring diode section has a pattern different from the pattern of the neighboring diode section in the top view is provided.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: August 2, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masahiro Taoka
  • Patent number: 11378545
    Abstract: A semiconductor structure capable of real-time spatial sensing of nanoparticles within a nanofluid is provided. The structure includes an array of gate structures. An interlevel dielectric material surrounds the array of gate structures. A vertical inlet channel is located within a portion of the interlevel dielectric material and on one side of the array of gate structures. A vertical outlet channel is located within another portion of the interlevel dielectric material and on another side of the array of gate structures. A horizontal channel that functions as a back gate is in fluid communication with the vertical inlet and outlet channels, and is located beneath the array of gate structures. A back gate dielectric material portion lines exposed surfaces within the vertical inlet channel, the vertical outlet channel and the horizontal channel.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: July 5, 2022
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 11374138
    Abstract: There is provided imaging devices and methods of forming the same, including a stacked structure body including a first electrode, a light-receiving layer formed on the first electrode, and a second electrode formed on the light-receiving layer, where the second electrode comprises an amorphous oxide comprising at least one of zinc and tungsten, and where the second electrode is transparent and electrically conductive and has absorption characteristics of 20% or more at a wavelength of 300 nm.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 28, 2022
    Assignee: SONY CORPORATION
    Inventor: Toshiki Moriwaki
  • Patent number: 11367655
    Abstract: A chip production method includes a first step of setting a first cutting line and a second cutting line on a substrate including a plurality of functional elements, a second step of forming a mask on the substrate such that the functional elements are covered and an intersection region including an intersection of the first cutting line and the second cutting line is exposed, a third step of removing the intersection region from the substrate and forming a penetration hole by etching the substrate using the mask, a fourth step of forming a modified region in the substrate along the first cutting line, a fifth step of forming a modified region in the substrate along the second cutting line, and a sixth step of forming chips by cutting the substrate along the first cutting line and the second cutting line.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: June 21, 2022
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomoya Taguchi, Takeshi Sakamoto
  • Patent number: 11296235
    Abstract: A thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display panel are provided. The thin film transistor includes an active layer and a wire grid which is disposed at least on a surface of an active region of the active layer and is made of a conductive material. The active layer includes a source region, a drain region, and the channel region between the source region and the drain region. The wire grid includes a plurality of wire grid sections which are spaced apart from each other, and in a direction from the source region to the drain region, a length of the channel region is longer than a length of the wire grid section.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: April 5, 2022
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Zhenhua Lv, Lianjie Qu, Yanfeng Wang, Hongbo Feng, Xuewen Lv, Jiantao Liu
  • Patent number: 11276733
    Abstract: An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers of memory cells and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors. The local second vertical line within individual of the pairs is in conductive connection with another of the two source/drain regions of the one select transistor. Individual of the memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Zengtao T. Liu
  • Patent number: 11244910
    Abstract: A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: February 8, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Karine Saxod, Marika Sorrieul
  • Patent number: 11233177
    Abstract: A package for mounting a light emitting element includes: a first lead electrode having, in a plan view, a first region, a second region surrounding a periphery of the first region having a width of 110 ?m or more and a thickness greater than that of the first region, and a third region partially surrounding a periphery of the second region and having a thickness smaller than that of the second region; a second lead electrode spaced apart from the first lead electrode; and a resin molded body fixing a portion of each of the first and second lead electrodes. A portion of each of the first and second lead electrodes and a portion of the resin molded body exposed therebetween form a bottom surface of a recess.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: January 25, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Koji Abe, Yuki Shiota
  • Patent number: 11222847
    Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Ravindranath V. Mahajan, Zhiguo Qian, Henning Braunisch, Kemal Aygun, Sujit Sharan
  • Patent number: 11211477
    Abstract: A FinFET and methods for forming a FinFET are disclosed. A method includes forming a semiconductor fin on a substrate, implanting the semiconductor fin with dopants, and forming a capping layer on a top surface and sidewalls of the semiconductor fin. The method further includes forming a dielectric on the capping layer, and forming a gate electrode on the dielectric.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Chih-Pin Tsao, Hou-Yu Chen
  • Patent number: 11201120
    Abstract: In embodiments of the present disclosure, there is provided a display substrate assembly including: a base substrate; a light shielding layer on the base substrate; and an active layer of a thin film transistor, above the base substrate. An orthographic projection of the active layer on the base substrate in a thickness direction of the base substrate is within an orthographic projection of the light shielding layer on the base substrate in the thickness direction of the base substrate, and the light shielding layer includes an ion-doped amorphous silicon layer. In embodiments of the present disclosure, there is also provided a method of manufacturing a display substrate assembly and a display apparatus including the display substrate assembly.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: December 14, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qi Yao, Zhanfeng Cao, Feng Zhang, Jiushi Wang
  • Patent number: 11139242
    Abstract: Integrated chips and methods for forming vias in the same include forming a multi-layer isolation structure on an underlying layer. The multi-layer isolation structure includes a first isolation layer around a second isolation layer. Conductive material is formed around the multi-layer isolation structure. The first isolation layer is etched back to expose at least a portion of a sidewall of the conductive material. A conductive via is formed to contact a top surface and the exposed portion of the sidewall of the conductive material.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: October 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Chih-Chao Yang, Chi-Chun Liu, Kangguo Cheng
  • Patent number: 11101290
    Abstract: A method for manufacturing a semiconductor memory device includes forming a first polysilicon layer on a conductive layer, forming a second polysilicon layer stacked on the first polysilicon layer, and forming a third polysilicon layer stacked on the second polysilicon layer. In the method, a stacked structure of the first, second and third polysilicon layers is patterned into a plurality of stacked structures spaced apart from each other on the conductive layer. Ferroelectric dielectric layers are formed on respective second polysilicon layers of the plurality of stacked structures, and metal layers are formed on the ferroelectric dielectric layers.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari
  • Patent number: 11101307
    Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Yu Lai, Min-Ying Tsai, Yeur-Luen Tu, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Patent number: 11043420
    Abstract: In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 22, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: George Chang, Yusheng Lin, Gordon M. Grivna, Takashi Noma
  • Patent number: 11043634
    Abstract: A semiconductor device with resistive memory includes a bottom electrode disposed on a base structure, the bottom electrode having a structure that tapers up from the base structure to a tip of the bottom electrode. The semiconductor device also includes sidewall spacers on the sides of the bottom electrode, an interlayer dielectric deposition (ILD) outside the sidewall spacers, and a top dielectric layer disposed over the bottom electrode, and the sidewall spacers. The semiconductor device further includes a top electrode deposited over the bottom electrode within the sidewall spacers. A filament formation region is formed at the tip of the bottom electrode.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: June 22, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dexin Kong, Takashi Ando, Kangguo Cheng, Juntao Li
  • Patent number: 11038149
    Abstract: A display panel and a mobile device are provided. The display panel includes a light-emitting substrate; and a photoresist layer disposed on the light-emitting substrate; wherein a scattering layer is disposed between the light-emitting substrate and the photoresist layer, such that light emitted by the light-emitting substrate passes through the scattering layer and exits from the photoresist layer through the scattering layer, and causes that external light passing through the photoresist layer, refracted and/or reflected by the scattering layer, is absorbed by the photoresist layer.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: June 15, 2021
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Wenjing Yu