Abstract: The disclosure provides an image sensor integrated chip and a method for forming the same. The image sensor integrated chip includes a substrate including a pixel region, an isolation structure disposed in the substrate and configured at opposite sides of the pixel region, an image sensing element disposed in the pixel region of the substrate, a gate structure disposed on the pixel region of the substrate, a first dielectric layer disposed above the pixel region of the substrate and covering sidewalls and a portion of a top surface of the gate structure, and a reflective layer disposed on the first dielectric layer. The reflective layer overlaps with the image sensing element and the portion of the top surface of the gate structure in a first direction perpendicular to a surface of the substrate.

Abstract: A device includes a substrate, a first semiconductor fin over the substrate extending in a first lateral direction, a first vertical stack of semiconductor nanosheets over the substrate extending in the first lateral direction, and an inactive fin between the first semiconductor fin and the first vertical stack extending in the first lateral direction. A first gate structure surrounds and covers the first semiconductor fin, and extends in a second lateral direction substantially perpendicular to the first lateral direction. A second gate structure surrounds and covers the first vertical stack, and extends in the second lateral direction.

Abstract: The present invention discloses structures and methods for making tiled displays for optoelectronic systems. The invention provides for a method of making a micro device tiled display. The method provides a tile substrate having a plurality of tiles. The method provides for a backplane layer. The method provides for covering a first surface of one of the backplane layer or the tile substrate with an adhesive. The method provides for aligning and releasing the tiles to the backplane. The method provides for curing the adhesive. The method provides for filling an area or a trench between the plurality of tiles and an area or trench between micro devices with a filler layer, wherein the filler layer is extended to either side of the tile depending on the view direction.

Abstract: An electronic apparatus includes a display panel that includes first electrodes connected to transistors, a second electrode disposed on the first electrodes, a plurality of light emitting patterns each being disposed on a corresponding first electrode, and reflective compensation electrodes spaced apart from the first electrodes. The display panel further includes light emitting areas in which the light emitting patterns are disposed, light transmitting areas in which transmission openings spaced apart from the light emitting patterns are formed through a portion of a circuit element layer and a display element layer, and reflective compensation areas in which the reflective compensation electrodes are disposed. The electronic apparatus includes further includes an electronic module disposed under the display panel and that overlaps the light transmitting areas and is spaced apart from the reflective compensation areas.

Abstract: A display device includes: a substrate; a bank layer on the substrate, and defining a light-emitting area; an organic light-emitting layer in the light-emitting area; a thin-film sealing layer covering the organic light-emitting layer and the bank layer; an inorganic layer including a base part on the thin-film sealing layer, and a protruding pattern part protruding from the base part in a thickness direction and including a lateral surface having a reverse taper angle; a first low refractive organic layer on the base part of the inorganic layer; and a high refractive organic layer covering the first low refractive organic layer and the inorganic layer. A lateral surface of the first low refractive organic layer contacts the lateral surface of the protruding pattern part, and an upper surface of the first low refractive organic layer protrudes more than an upper surface of the protruding pattern part in the thickness direction.

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a first electronic component, a second electronic component, a bonding wire, and an encapsulant. The substrate has a lower surface and an upper surface opposite to the lower surface. The first electronic component is disposed on the upper surface of the substrate. The bonding wire electrically connects the first electronic component and the substrate and extends within the substrate. The second electronic component is disposed on the upper surface of the substrate. The second electronic component has an active surface facing the substrate. The encapsulant is disposed on the upper surface of the substrate. The encapsulant extends within the substrate and encapsulates the bonding wire.

Abstract: A package for mounting a light emitting element includes: a first lead electrode defining a portion of a bottom of a recess and comprising a base member and a plating disposed on the base member, and wherein the first lead electrode comprises, in a plan view: a first region, a second region surrounding a periphery of the first region, wherein, in a height direction, an upper surface of the base member in an entirety of the second region is higher than an upper surface of the base member in the first region, and a third region surrounding at least a portion of a periphery of the second region, wherein, in the height direction, an upper surface of the base member in the third region is lower than the upper surface of the base member in the entirety of the second region; a second lead electrode; and a resin molded body.

Abstract: An electrically erasable programmable read only memory (EEPROM) includes a substrate, isolation structures, a row of erase gate and a row of floating gates. The isolation structures are defined in the substrate to extend in a first direction. The row of erase gate having a wave shape is disposed across the substrate. The row of floating gates having staggered islands is disposed parallel to the row of erase gate. A method of forming said electrically erasable programmable read only memory (EEPROM) is also provided.

Abstract: The disclosure provides a display panel and a display device. The display panel includes a first substrate and a second substrate, the second substrate has an organic electroluminescent device, an anode layer of the organic electroluminescent device is away from the first substrate and a cathode layer thereof is closer to the first substrate than the anode layer; the cathode layer is electrically connected to an auxiliary electrode on a light entering surface of the first substrate through multiple conductive spacers, the cathode layer is a transparent electrode layer; the auxiliary electrode has a resistance smaller than that of the cathode layer of the organic electroluminescent device; the auxiliary electrode is a grid-shaped auxiliary electrode and in a non-display region, the auxiliary electrode is opaque; the multiple conductive spacers includes first conductive spacers on the auxiliary electrode and second conductive spacers on the cathode layer of the second substrate.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a circuit area and a non-circuit area; a top dielectric layer positioned on the substrate; a top interconnector positioned along top dielectric layer and above the circuit area; a cushion structure positioned along the top dielectric layer and above the non-circuit area; a bottom passivation layer positioned on the top dielectric layer; a top conductive pad positioned in the bottom passivation layer and on the top interconnector; a redistribution layer positioned on the top conductive pad, on the bottom passivation layer, and extending from the circuit area to the non-circuit area; and an external connector positioned on the redistribution layer and above the cushion structure. The cushion structure includes a porous polymeric material.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a circuit area and a non-circuit area; a top dielectric layer positioned on the substrate; a top interconnector positioned along top dielectric layer and above the circuit area; a cushion structure positioned along the top dielectric layer and above the non-circuit area; a bottom passivation layer positioned on the top dielectric layer; a top conductive pad positioned in the bottom passivation layer and on the top interconnector; a redistribution layer positioned on the top conductive pad, on the bottom passivation layer, and extending from the circuit area to the non-circuit area; and an external connector positioned on the redistribution layer and above the cushion structure. The cushion structure includes a porous polymeric material.

Abstract: In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.

Abstract: A manufacturing method of a semiconductor structure includes the following operations. A substrate is provided, which includes a first N region, a first P region, a second N region and a second P region adjacently arranged in sequence. A gate dielectric layer, a first barrier layer, a first work function layer and a second barrier layer are formed on the substrate in sequence. A mask layer is formed on the second barrier layer of the first P region and the second P region. The second barrier layer of the first N region and the second N region is removed by a first etching process with the mask layer as a mask. The first work function layer and the first barrier layer of the first N region and the second N region are removed by a second etching process. A semiconductor structure is also provided.

Abstract: A method is provided for modifying a strain state of a block of a semiconducting material including steps in the following order: a) making a lower region of the block of the semiconducting material resting on a substrate amorphous, while a crystalline structure of an upper region of the block in contact with the lower region is maintained, then b) forming a stressing zone on the block of the semiconducting material, then c) making at least one creep annealing with a suitable duration and temperature to enable creep of the lower region without recrystallizing a material of the lower region, and then d) making at least one recrystallization annealing of the lower region of the block.

Abstract: The application relates to a manufacture method of a high-resistivity silicon handle wafer for a hybrid substrate structure. The method comprises a step of producing the wafer having a crystal orientation identifier and a certain thickness. The method further comprises a step of thinning the produced wafer from the certain thickness to a desired thickness of the wafer in order to obtain the thinned wafer. The method further comprises a step of providing a surface passivation layer having a certain layer thickness on a front surface of the thinned wafer. The method further comprises a step of polishing the passivation layer from the certain layer thickness to a desired final layer thickness of the passivation layer so that the polished front surface of the wafer enables active layer bonding in order to form the hybrid substrate structure.

Abstract: An array of vertically stacked tiers of memory cells includes horizontally oriented access lines within individual tiers of memory cells and horizontally oriented global sense lines elevationally outward of the tiers. Select transistors are elevationally inward of the tiers. Pairs of local first and second vertical lines extends through the tiers. One vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors. The second vertical line within individual of the pairs is in conductive connection with another of the two source/drain regions of the one select transistor. Individual of the memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects including methods, are disclosed.

Abstract: A semiconductor device assembly is provided. The assembly includes a first semiconductor die and a second semiconductor die disposed over the first semiconductor die. The assembly further includes a plurality of die support structures between the first and second semiconductor dies and a plurality of interconnects between the first and second semiconductor dies. Each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them. Each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them. The first solder joint thickness is less than the second solder joint thickness.

Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Abstract: A bit cell structure for one-time programming is provided in the present invention, including a substrate, a first doped region in the substrate and electrically connecting a source line, a second doped region in the substrate and having a source and a drain electrically connecting a bit line, a heavily-doped channel in the substrate and connecting the first doped region and the source of second doped region, and a word line crossing over the second dope region between the source and the drain.

Abstract: Photosensors may be formed on a front side of a semiconductor substrate. An optical refraction layer having a first refractive index may be formed on a backside of the semiconductor substrate. A grid structure including openings is formed over the optical refraction layer. A masking material layer is formed over the grid structure and the optical refraction layer. The masking material layer may be anisotropically etched using an anisotropic etch process that collaterally etches a material of the optical refraction layer and forms non-planar distal surface portions including random protrusions on physically exposed portions of the optical refraction layer. An optically transparent layer having a second refractive index that is different from the first refractive index may be formed on the non-planar distal surface portions of the optical refraction layer. A refractive interface refracts incident light in random directions, and improves quantum efficiency of the photo sensors.