Abstract: Various embodiments provide semiconductor structures and their fabrication methods. An SRAM memory cell can include at least one semiconductor structure, and an SRAM memory can include at least one SRAM memory cell. An exemplary semiconductor structure can include at least two adjacent transistors formed on a semiconductor substrate. An opening can be formed and surrounded by gates of the two adjacent transistors and a doped region formed between the gates of the two adjacent transistors. A conductive layer can be formed to at least partially cover a bottom and a sidewall of the opening to electrically connect a gate of one transistor with the doped region of the other transistor of the two adjacent transistors.

Abstract: The invention provides a display panel and a manufacturing method thereof, and a display device, belongs to the field of display device manufacturing technology, which can solve the following problem in the existing display device: when light transmits the cathode layer which is thin, has high resistance and thus poor conductivity, the display effect is nonuniform. The display panel of the invention comprises a first substrate and a second substrate which are assembled, wherein the second substrate is provided with an organic electroluminescent device thereon, an anode layer of the organic electroluminescent device is away from the first substrate and an cathode layer thereof is close to the first substrate; and the cathode layer is electrically connected to an auxiliary electrode on a light entering surface of the first substrate through a plurality of conductive spacers spaced at certain intervals, wherein the cathode layer is a transparent electrode layer.

Abstract: The field-effect mobility of a semiconductor device is improved, and the on-state current thereof is increased, so that stable electrical characteristics are obtained. The semiconductor device includes a first oxide insulator, an oxide semiconductor, and a second oxide insulator which are stacked. The first oxide insulator includes In, Zn, and M (M represents Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), and the content of In is lower than the content of M, and the content of In is lower than the content of Zn. The oxide semiconductor includes In and M (M represents Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), and the content of In is higher than the content of M. The second oxide insulator includes In, Zn, and M (M represents Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf).

Abstract: A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material.

Abstract: The embodiments of the invention disclose an array substrate, a manufacturing method thereof and a display device. Due to the fact that the surfaces of a source electrode, a drain electrode and a data line which are arranged on the same layer are provided with an oxide film which is formed after annealing treatment is conducted on the source electrode, the drain electrode and the data line, in the process that the pattern of a pixel electrode is formed on the source electrode, the drain electrode and the data line by the adoption of a composition technology, the oxide film can protect the source electrode and the data line under the oxide film from being corroded by an etching agent when the pattern of the pixel electrode is formed by etching, and the display quality of a display panel will not be affected.

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.

Abstract: A radiation detector (10) which has a multilayer structure that includes: a first electrode (34); a second electrode (49) that is disposed so as to face the first electrode; a selenium layer (48) that is disposed between the first electrode and the second electrode and contains amorphous selenium; a first blocking organic layer (38) that is adjacent to the selenium layer, between the first electrode and the selenium layer, and that contains a hole transport material having an electron affinity of 3.7 eV or less; and a second blocking organic layer (37) that is adjacent to the selenium layer, between the second electrode and the selenium layer, and that contains an electron transport material having an ionization potential of 5.9 eV or more. This radiation detector (10) has low dark current, excellent durability, and less afterimages.

Abstract: A method for forming a semiconductor device includes forming first fins from a first semiconductor material and second fins from a second semiconductor material and encapsulating the first fins and the second fins with a protective dielectric. Semiconductor material between the first fins and the second fins is etched to form trenches. A dielectric fill is employed to fill up the trenches, between the first fins and between the second fins. The first semiconductor material below the first fins and the second semiconductor material below the second fins are oxidized with the first and second fins being protected by the protective dielectric. Fins in an intermediary region between the first fins and the second fins are oxidized to form dummy fins in the intermediary region to maintain a substantially same topology across the device.

Abstract: An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the source/drain regions of one of the select transistors. The local second vertical line is in conductive connection with the other source/drain region of the one select transistor. Individual memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects and implementations, including methods, are disclosed.

Abstract: A package for mounting a light emitting element includes: a first lead electrode having, in a plan view, a first region, a second region surrounding a periphery of the first region having a width of 110 ?m or more and a thickness greater than that of the first region, and a third region partially surrounding a periphery of the second region and having a thickness smaller than that of the second region; a second lead electrode spaced apart from the first lead electrode; and a resin molded body fixing a portion of each of the first and second lead electrodes. A portion of each of the first and second lead electrodes and a portion of the resin molded body exposed therebetween form a bottom surface of a recess.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate oxide film, and a gate electrode. A trench is provided in the main surface to have a side surface and a bottom portion. A contact point between a first side surface portion and a second side surface portion is located in a third impurity region. An angle formed by the first side surface portion and a straight line extending through the contact point and parallel to the main surface is smaller than an angle formed by the second side surface portion and a boundary surface between a first impurity region and a second impurity region. A thickness of a portion of the gate oxide film on the contact point between the main surface and the first side surface portion is larger than a thickness of a portion of the gate oxide film on the second impurity region.

Abstract: A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring.

Abstract: A light emitting device includes a p-side heterostructure having a short period superlattice (SPSL) formed of alternating layers of AlxhighGa1-xhighN doped with a p-type dopant and AlxlowGa1-xlowN doped with the p-type dopant, where xlow?xhigh?0.9. Each layer of the SPSL has a thickness of less than or equal to about six bi-layers of AlGaN.

Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.

Abstract: Provided is a flexible device with fewer defects caused by a crack or a flexible device having high productivity. A semiconductor device including: a display portion over a flexible substrate, including a transistor and a display element; a semiconductor layer surrounding the display portion; and an insulating layer over the transistor and the semiconductor layer. When seen in a direction perpendicular to a surface of the flexible substrate, an end portion of the substrate is substantially aligned with an end portion of the semiconductor layer, and an end portion of the insulating layer is positioned over the semiconductor layer.

Abstract: An antifuse structure includes a first electrode layer, an inter-metal dielectric layer over the first electrode layer, and a via in the inter-metal dielectric layer. The via penetrates through the inter-metal dielectric layer exposing a portion of the first electrode layer. An antifuse layer is deposited in the via and over the portion of the first electrode layer. A second electrode is disposed in the via and over the antifuse layer. An interconnect layer may be deposited over the inter-metal dielectric layer and in electrical contact with the second electrode in the via.

Abstract: A light emitting diode (LED) structure including a stacked semiconductor layer, a contact layer and a dielectric reflective layer is provided. The stacked semiconductor layer includes a first type doped layer, a second type doped layer and an active layer disposed between the first type doped layer and the second type doped layer, wherein the first type doped layer, the active layer and the second type doped layer are penetrated by a plurality of recesses. The contact layer is disposed on the second type doped layer. The dielectric reflective layer is disposed on the contact layer and extended into the recesses to connect the contact layer and the first type doped layer with a coverage rate equal to or less than 60% from a top view of the LED structure.

Abstract: A combing bump structure includes a semiconductor substrate, a pad, a conductive layer, a solder bump and at least two metal side walls The pad is disposed on the semiconductor substrate. The conductive layer is disposed on the pad. The solder bump is disposed on the conductive layer. The at least two metal side walls are disposed along opposing outer side walls of the solder bump respectively.

Abstract: A semiconductor device includes a semiconductor substrate and a fin positioned above the semiconductor substrate, wherein the fin includes a semiconductor material. Additionally, a ferroelectric high-k spacer covers sidewall surfaces of the fin and a non-ferroelectric high-k material layer covers the ferroelectric high-k spacer and the fin, wherein a portion of the non-ferroelectric high-k material layer is positioned on and in direct contact with the semiconductor material at the upper surface of the fin.