Abstract: A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the same are disclosed. Embodiments of the invention provide a pixel cell comprising a substrate. A gate of a transistor is formed at least partially below the surface of the substrate and a photodiode is adjacent to the gate. The photodiode comprises a doped surface layer of a first conductivity type, and a doped region of a second conductivity type underlying the doped surface layer. The doped surface layer is at least partially above a level of the bottom of the gate.

Abstract: A new post-passivation metal interconnect scheme is provided over the surface of a IC device that has been covered with a conventional layer of passivation. The metal scheme of the invention comprises, overlying a conventional layer of passivation, thick and wide metal lines in combination with thick layers of dielectric and bond pads. The interconnect system of the invention can be used for the distribution of power, ground, signal and clock lines from bond pads to circuits of a device that are provided in any location of the IC device without introducing significant power drop. The post passivation metal scheme is connected to external circuits through bond pads, solder bonding, TAB bonding and the like. A top layer of the interconnect metal scheme is formed using a composite metal for purposes of wirebonding, the composite metal is created over a bulk conduction metal.

Abstract: A die is unpackaged from a Chip on Tape by grinding off molding compound from an upper surface of the COT until the COT's leads are evenly exposed across the upper surface, selectively etching out the leads using the remaining molding compound as a mask, removing an underlying layer of gold plating, and then removing the remaining molding compound. The unpacked die can then be reframed with new leads and molding compound for failure analysis and electrical failure verification.

Abstract: Provided with a method of manufacturing a ball grid array semiconductor package using a flexible circuit board strip, which is directed to prevent minute conductive traces in the outer part of a circuit pattern formed in the flexible circuit board and thus minimize the short-circuits by forming notches on the flexible circuit board in the vicinity of the lower side ends of a resin encapsulant section by use of a punch, and pressing down the resin encapsulant section with a singulation tool to remove the carrier frame and separate the ball grid array semiconductor packages in the piece.

Abstract: A method of scribing and separating chips on a semiconductor wafer (21) wherein the wafer (21) is patterned and a pattern of intersecting grooves is etched on a selected surface of the semiconductor wafer (21) in a pattern, preferably in a grid pattern, to define chip areas on that surface. Trenches (27) are then formed in the shape of the pattern and the selected surface is adhered to a tape (29). Light is then passed through the tape (29) and semiconductor wafer (21) from the pattern and a pattern of intersecting saw cuts or grooves (28) aligned with the light passing through the wafer (21) is formed. The saw cuts (28) extend from a surface of the wafer (21) opposing the selected surface and are aligned with the pattern of intersecting trenches (27).

Abstract: Semiconductor package and method in which a chip is mounted in an opening in a frame with the back side of the chip facing outside the package, and a heatsink is positioned in direct thermal contact with the back side of the chip. In one preferred method of manufacture, the chip is mounted in the frame and tested before the heatsink is attached.

Abstract: A vertical-cavity surface-emitting laser (VCSEL) has an active region, first and second mirror stacks forming a resonant cavity with a radial variation in index forming a transverse optical mode, and a thin insulating slot within the cavity to constrict the current to a diameter less than the beam waist of the optical mode thereby improving device efficiency and preferentially supporting single mode operation. In one embodiment, an insulating slot is formed by etching or selectively oxidizing a thin aluminum-containing semiconductor layer in towards the center of a cylindrical mesa. The slot thickness is sufficiently thin that the large index discontinuity has little effect on the transverse optical-mode pattern. The slot may be placed near an axial standing-wave null to minimize the perturbation of the index discontinuity and allow the use of thicker slots.

Abstract: A method for manufacturing and mounting a semiconductor device in which a void in a bonding portion is eliminated. A material which is to be formed into a protruding electrode is placed on a semiconductor element. The protruding electrode material is heated in a depressurized atmosphere so as to be melted. Then, the protruding electrode material is heated in a pressurized atmosphere which provides a pressure greater than a pressure in said depressurized atmosphere. Finally, the protruding electrode material is cooled so as to be solidified while the pressurized atmosphere is maintained. The semiconductor device is mounted to a mount board after a surface layer is electroplated on an electrode of the mount board.

Abstract: A process of cleaning debris (24) from a partially-sawn semiconductor wafer (10). The method of the present invention includes cleaning a partially fabricated wafer (12) that may have fabricated on it a micromechanical device (16) which can be easily damaged by particles (24) generated by the partial-saw process, such as oxide particles. The present invention includes cleaning the partially-sawn wafer with a solution including diluted hydrofluoric acid and an alkyl glycol. Clean-up using this solution accomplishes two goals. First, it removes debris including oxide particles on the wafer surface and in the kerfs (22), and second, reduces the depth of damage in the surface (26) of a CMOS layer (14) proximate the kerf (22) which has been determined to be a source of particles generated after a wafer cleanup process. A subsequent megasonic process is utilized to acoustically vibrate the wafer while bathed in deionized water to further remove any other particles.

Abstract: Thin-film transistors each having a different characteristic are selectively formed on the same substrate. A silicon oxide film, an amorphous silicon film, a barrier film for preventing the diffusion of a nickel element and an oxide film containing a nickel element that promotes the crystallization of silicon are sequentially formed on a glass substrate. The oxide film containing the nickel element is patterned and subjected to a heat treatment, to thereby crystallize the amorphous silicon film under the oxide film whereas the amorphous silicon film from which the oxide film has been removed remains as it is. After the heat treatment has been conducted, a laser light is irradiated on those films. On the silicon film which has been crystallized by heating, a laser light is irradiated in a state where even a necessary energy density is attenuated after the laser light transmits the oxide film, thereby promoting the crystalline property.

Abstract: A method of manufacturing semiconductor wafers using a simulation tool to determine predicted wafer electrical test measurements. The simulation tool combines in-line critical dimensions from previous from previous processes run on the current wafer lot, data from previous lots for processes subsequent to the process being run on the current lot and calibration simulation data obtained from the comparison of the predicted wafer electrical test measurements and collected wafer electrical test measurements taken from previous actual wafer electrical test measurements.

Abstract: An electronic packaging module for inverted bonding of semiconductor devices, integrated circuits, and/or application specific integrated circuits is produced with protuberances on the conductive pattern of the substrate. The protuberances are of a soft, ductile metal capable of being metallurgically bonded to the input/output pads of semiconductor devices. The input/output pads of the semiconductor devices are simultaneously bonded to the protuberances of the packaging module.

Abstract: Disclosed is an integrated circuit configuration including a carrier having recesses for supporting individual semiconductor die units. The semiconductor die units and the carrier recesses have lithographically defined dimensions so as to enable precise alignment and a high level of integration.

Abstract: A method of manufacturing a semiconductor device which allows reliability of connection to be improved and manufacturing time to be reduced includes sandwiching a sheet-shaped unhardended hardenable material between a semiconductor chip and an interposer or substrate. The hardenable material is then melted, thereby sealing the semiconductor chip and the interposer, including along connection terminals therebetween. The hardenable material is then hardened in an appropriate manner.

Abstract: A method is devised for packaging semiconductor chips based on a lead-on-chip (LOC) architecture which allows the size of the package to be substantially close to the chip size so as to reduce the packaging size to the minimum. The semiconductor chip is mounted based on a lead-on-chip architecture on a leadframe having a plurality of leads, a side rail, and at least a first connecting piece and a second connecting piece. In this method, the first step is to attach a ring to the leadframe. Then, the semiconductor chip is mounted on the leadframe and a plurality of wires are interconnected between the bonding pads on the semiconductor chip and the leads on leadframe. After that, a liquid epoxy is applied to the semiconductor chip so as to form a molding compound encapsulating the semiconductor chip. Finally, the side rail of the leadframe is removed from the leadframe. The step of encapsulation can be implemented either by epoxy dispensing or by print encapsulation system (PES).

Abstract: A hybrid chip having at least two different types of semiconductor devices co-located on a common substrate, and a method therefor, are disclosed. The devices have different multiple epitaxial layer structures so that each different type of device is first grown on a separate appropriately-selected substrate, and then attached to the common substrate. According to the method, a first device is attached to the common substrate using flip-chip bonding methods. Flip-chip bonding involves attaching the device and the substrate at bonding pads, flowing a flowable hardener between the first device and the common substrate and allowing it to harden, and then removing the substrate upon which the first device was grown. The hardener is removed before attaching the second type of device via flip-chip bonding.

Abstract: In a method for producing a circuit board for a semiconductor package, portions of the resist film formed on the respective surface of the core substrate are removed during the exposure/development process, which portions correspond to the circuit pattern and to the cavity opening but having a diameter smaller than that of the cavity opening, whereby the photosensitive portion of the resist film is hardened while extending inward from the upper edge of the cavity opening to a predetermined distance. The resist film operates as a resist for the conductor layer to be formed on the inner wall of the cavity opening and connected to the circuit pattern on one surface of the core substrate. Thereby, since the finally formed conductor layer does not reach the upper edge of the cavity opening at a predetermined vacant space therefrom, short-circuiting of the signal line is prevented from occurring even if the bonding wire is brought into contact with the upper edge of the cavity opening.

Abstract: Separate and distinct conductive layers for power and ground are insulated from one another and a patterned signal conductive layer to form a flexible substrate for mounting a semiconductor die in a semiconductor device assembly. TAB technology is utilized to produce an assembly that has superior electrical characteristics because power and ground is conducted on separate low impedance conductive layers. The power and ground leads connecting the semiconductor die and external circuits are selected from the signal trace layer, cut bent downward and attached by bonding to the respective power or ground layer. A tool is disclosed for cutting the selected leads. A method of attaching solder balls to a TBGA film using solder flux and photoimageable solder resist definition is also disclosed.

Abstract: A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the silicided region of the lower polycrystalline silicon layer.

Abstract: A semiconducting processing method for making electrical contacts with an active area in sub-micron geometries includes: (a) providing a pair of conductive runners on a semiconductor wafer; (b) providing insulative spacers on the sides of the conductive runners wherein adjacent spacers are spaced a selected distance apart at a selected location on the wafer; (c) providing an active area between the conductive runners at the selected location; (d) providing an oxide layer over the active area and conductive runners; (e) providing a planarized nitride layer atop the oxide layer; (f) patterning and etching the nitride layer selectively relative to the oxide layer to define a first contact opening therethrough, wherein the first contact opening has an aperture width at the nitride layer upper surface which is greater than the selected distance between the insulative spacers; (g) etching the oxide layer within the first contact opening to expose the active area; (h) providing a polysilicon plug within the first co