Abstract: A semiconductor device includes a semiconductor chip (11) having a top surface and a bottom surface, a plurality of leads (14) arranged under the bottom surface of the semiconductor chip (11), where the leads (14) have first ends (14a) electrically coupled to the semiconductor chip (11) and second ends which form external terminals (16) and each of the external terminals have a bottom surface, and a package (17, 31) encapsulating the semiconductor chip (11) and the leads (14) so that the bottom surface of each of the external terminals (16) is exposed at a bottom surface (17a, 31a) of the package (17, 31) and remaining portions of the leads (14) are embedded within the package (17, 31), where the package (17, 31) has a size which is approximately the same as that of the semiconductor chip (11) in a plan view viewed from above the top surface of the semiconductor chip (11).

Abstract: In the case of a method for producing a power semiconductor module (10), in which a plurality of submodules (12) are arranged on a common support (11), are interconnected by means of a multilayer laminate made of metal layers (13-15) and insulating layers (16, 17), which layers are layered alternately one above the other, and can be externally connected, reliable production of the laminate is achieved by virtue of the fact that in order to construct the laminate, the individual metal layers (13-15) and insulating layers (16, 17) are stacked one above the other, are aligned with one another and with respect to the support (11) by means of auxiliary alignment means (18, 19) and are interconnected in the aligned state by techniques such as welding, soldering or bonding.

Abstract: A method of counting semiconductor integrated circuit devices comprising steps of forming a semiconductor device block having a plurality of semiconductor integrated circuit devices of vertical mounting type coupled to each other in parallel, and mounting the semiconductor device block on a printed board. A block of semiconductor integrated circuit devices comprising a plurality of semiconductor integrated circuit devices of vertical mounting type, and coupling means for coupling the plurality of semiconductor integrated circuit devices each other in parallel.

Abstract: A method of making a temporary connection to an unpackaged semiconductor die, removing the temporary connection and preparing the site of the temporary connection to receive a permanent connection.

Abstract: The use of a test chip having a wide channel MOSFETs of different channel widths and effective gate lengths allows for an experimental determination of the fringe capacitance per unit width. The use of channel widths greater than 100 microns increases the accuracy of the measured capacitance values.

Abstract: A package such as for an image sensing device includes the device, which preferably is a solid state image sensing device converting an optical image to an electric signal, metal bumpers formed on the bonding pads of the image sensing device, leads electrically connected to the bumpers, a dielectric wall hermetically sealing the connection areas of the leads and the bumpers, and surrounding the circumference of a light-receiving region of the image sensing device, a glass lid attached onto the dielectric wall and thereby sealing the light-receiving region, and a package body enclosing the structure except the top surface of the glass lid and an exterior portion of the leads.

Abstract: A method of forming a semiconductor memory device comprises the steps of providing a semiconductor die, forming a temporary protective material over a surface of the die, and attaching the die to a first lead frame portion. Next, a protective material is contacted with a second lead frame portion and, subsequently, the second lead frame portion is electrically connected with the second lead frame portion with bond pads on the first surface of the die with bond wires. Subsequent to electrically connecting the die and the second lead frame portion the protective material is removed.

Abstract: A package for a high power semiconductor laser comprising a hermetically sealed container filled with a dry gaseous medium containing oxygen. The presence of oxygen in the laser atmosphere is counter to standard practice in the art which teaches the use of an atmosphere of a dry inert gas. The package also includes a getter for organic impurities, e.g., a getter composed of a porous silica or a zeolite. The hydrogen content of the materials used to form the package are reduced by baking at an elevated temperature for an extended period of time, e.g., at 150.degree. C. for 200 hours.

Abstract: A circuit pattern 2a, made of copper foil, is arranged on a substrate 1. A nickel-containing barrier metal layer 2b is formed on the.circuit pattern 2a. A gold layer 2c is formed on the barrier metal layer 2b by electroless substitution plating. Then, substrate 1 is heated up to impel nickel contained in the gold layer 2c to move toward a surface zone of the gold layer 2c to deposit nickel compound in the surface zone of the gold layer 2c, thereby enhancing the fineness of a remaining part of the gold layer 2c at at least an inside zone immediately below the surface zone. Then, the surface zone containing the crowded nickel compound is removed off the gold layer 2c so as to expose a purified surface of the inside zone of the gold layer 2c. Therefore, it becomes possible to form an excellent electrode having satisfactory bondability to the wire by using a less amount of gold at low costs.

Abstract: According to the invention, a packaged integrated circuit includes a lid attached to a base to enclose a cavity, an integrated circuit chip or chips being attached to each of the lid and base within the cavity. Preferably, the chip or chips that generate the most heat during operation of the packaged integrated circuit are attached to the lid and the lid is made of a material having good thermal conductivity such as aluminum nitride. The chips attached to the base generate relatively little heat and so do not require a heat sink to be included in the base. The packaged integrated circuit is formed in a cavity-up configuration, thereby enabling connection pins or solder balls to be formed over the entire exterior surface of the base, increasing interconnection density. Additionally, attachment of chips to both the lid and the base allows an increased number of electronic functions to be included in one packaged integrated circuit.

Abstract: The method of manufacturing a solid state imaging device of the invention comprises a step of adding carboxylate as a dyeing assistant auxiliary to the aqueous dyestuff solution when forming dyeing layers of acrylic-based resin on a semiconductor substrate on which a solid state imaging element is formed. Therefore this invention provides a solid state imaging device with a color filter which is dyed densely, is flat, thin, and excellent in spectral characteristics. A transparent planarization resin layer (the material is e.g. acrylic) is formed on a semiconductor substrate, and a shading layer and a planarization resin layer are successively formed thereon. A synthetic resin is prepared and added photosensitizer of diazo compound. On the above-mentioned planarization resin layer, the layer of the synthetic resin is coated to be 0.2 to 0.8 .mu.m thick, for example, by a spin coat method. Then the synthetic resin is selectively exposed with a stepper, and developed to form patterns of a color filter.

Abstract: A printed wiring board with either a pin grid array, a ball grid array, a land grid array, etc. of electrical contacts is prepared with a heat sink in the usual manner. A passage is provided either in the printed wiring board or in the heat sink so that during the transfer molding process, fluid molding compound passes latitudinally under the heat sink into a cavity below the heat sink to encapsulate the package.

Abstract: A method for fabricating solder bumps on a microelectronic device having contact pads includes the steps of depositing a titanium barrier layer on the device, forming an under bump metallurgy layer on the titanium barrier layer, and forming one or more solder bumps on the under bump metallurgy layer. The solder bump or bumps define exposed portions of the under bump metallurgy layer which are removed, and then the exposed portion of the titanium barrier layer is removed. The titanium barrier layer protects the underlying microelectronic device from the etchants used to remove the under bump metallurgy layer. The titanium layer also prevents the under bump metallurgy layer from forming a residue on the underlying microelectronic device. Accordingly, the titanium barrier layer allows the under bump metallurgy layer to be quickly removed without leaving residual matter thereby reducing the possibility of electrical shorts between solder bumps.

Abstract: A device module with a circuit chip and a print-circuit substrate on which a pattern of grooves is formed by selective etching. A liquid sealing material is in the space between the circuit chip and the surface of the substrate, fixing the circuit chip on the surface of the substrate. The circuit chip has a plurality of electrodes arranged in a first pattern, and the substrate has a plurality of connection terminals arranged in the first pattern within a chip mounting area on a surface thereof. Each of the grooves passes between two adjacent connection terminals through the chip mounting area, and both ends of each groove protrudes from the periphery of the chip mounting area. After the circuit chip is placed on the chip mounting area with the respective electrodes corresponding to the connection terminals, a liquid sealing material may be spread more easily into the space between the circuit chip and the substrate by the use of capillary action to provide a more reliable and efficient seal.

Abstract: A solid tape automated bonding method includes steps of: applying a pattern of a first dry film on a first portion of a copper plate; forming wiring; forming bumps; removing dry film and exposing the wiring and the bumps; selectively laminating an insulator layer onto portions of the exposed copper plate and the wiring; laminating a metal layer on the insulator layer; applying glue on the metal layer, the bumps, and respective exposed portions of the wiring and the copper plate; etching the copper plate thus exposing one side of the wiring as ball pads and exposing one side of the insulator layer; coating solder resist on the exposed bottom side of the insulator layer; removing the glue; attaching a die against the bumps; applying mold compound onto the die so as to fix the die in place; and attaching solder balls onto the ball pads. This method provides relatively high density of wiring and simplification in manufacturing.

Abstract: A method and encapsulation material are provided for processing an electronic circuit assembly having surface mount integrated circuit packages mounted with soldered leads to its substrate, in which encapsulation of the soldered lead joints serves to enhance the fatigue life of the solder joints. The encapsulation material is a reactive hot melt epoxy that is curable at temperatures significantly lower than that required for previous epoxy-based encapsulation materials. As such, processing of the circuit assembly is greatly facilitated, while the benefit of encapsulated solder joints is achieved for the assembly. The encapsulation material further includes a latent curative and a filler material for lower the coefficient of thermal expansion of the encapsulation material.

Abstract: A method for producing a semiconductor element, comprising treating a lead frame or a semiconductor wafer or a semiconductor chip, or a lead frame and a semiconductor chip in combination, with at least one package crack-preventing compound selected from compounds having a reactive group, acids, derivatives at a group due to which said acid assumes acidity, siloxane derivatives of the formula (I) ##STR1## and compounds having a number average molecular weight of not more than 10,000 and comprising, in their structure, said siloxane derivative; and an adhesive for adhering a wafer, which is usable in said production method. According to the method, package cracks can be significantly prevented.

Abstract: A process for fabricating a solder bump having an improved geometry includes the steps of evaporatively depositing a first metallization system to form a post having a predetermined volume onto an integrated circuit having a passivation layer defining a die pad window, wherein the length of the post is greater than the width of the post, and wherein the length of the post extends beyond the die pad window over the passivation layer, and evaporatively depositing a second metallization system onto the post to form a cap also having a volume, wherein the first metallization system forming the post and the second metallization system forming the cap, when reflowed, form a eutectic solder bump.

Abstract: A method of making an electronic module with an integrated circuit includes beginning with a standardized starting product in the form of an insulating substance bearing a conductive coating. Contact surfaces are formed in the conductive coating by interruptions in the insulating substance. Using milling cutter one provides the insulating layer of the starting product with variable patterns of recesses through which conductive connections between the contact surfaces and the integrated circuit are later guided. The position of the recesses is varied in accordance with the size of the integrated circuit to be incorporated in the electronic module.

Abstract: In a fabricating method of an optical semiconductor device, a pair of SiO.sub.2 films are formed on an n-InP substrate so as to have a large width in a region I (laser region) and a small width in a region II (optical waveguide region) and have the same gap interval therebetween in the regions I and II, and then an InGaAsP optical guide layer, a MQW (multiquantum well) active layer comprising InGaAsP quantum well layers and InGaAsP barrier layers, and a p-InP layer are selectively grown by MOVPE (metal-organic vapor phase epitaxial growth) method, whereby compressive lattice strain is introduced in the InGaAsP quantum well layers of the region I, and tensile lattice strain is introduced in the InGaAsP quantum well layers of the region II.