Abstract: Bulk scaling out of a geographically diverse storage system is disclosed. Bulk scaling out can result in addition of at least two zone storage components to the geographically diverse storage system. Bulk scaling out can provide an avenue to move and compact data to benefit the geographically diverse storage system. Benefits can include faster access to data, faster recovery time for data that becomes less accessible, reduced computing resource demands, etc. Chunks can be moved for greater diversity in a bulk scaled out system. The greater diversity can allow for compaction of data protection chunks, which can result in consuming less storage space to protect more diversified data storage. In some embodiments data from existing zone storage components can be moved to added zone storage components. In some embodiments, protection data from existing zone storage components can be moved to added zone storage components in a more compacted condition.

Abstract: In response to a cache flush event indicating that host data accumulated in a cache of a storage processor of a data storage system is to be flushed to a lower deck file system, an aggregation set of blocks is formed within the cache, and a digest calculation group is selected from within the aggregation set. Hardware vector processing logic is caused to simultaneously calculate crypto-digests from the blocks in the digest calculation group. If one of the resulting crypto-digests matches a previously generated crypto-digest, deduplication is performed that i) causes the lower deck file system to indicate the block of data from which the previously generated crypto-digest was generated and ii) discards the block that corresponds to the matching crypto-digest. Objects required by a digest generation component may be allocated in a just in time manner to avoid having to manage a pool of pre-allocated objects.

Abstract: In a computer network in which a data storage array maintains data for at least one host computer, the host computer provides sequential access hints to the storage array. A monitoring program monitors a host application running on the host computer to detect generation of data that is likely to be sequentially accessed by the host application along with associated data. When the host application writes such data to a thinly provisioned logical production volume the monitoring program prompts a multipath IO driver to generate the sequential access hint. In response to the hint the storage array allocates a plurality of sequential storage spaces on a hard disk drive for the data and the associated data. The allocated storage locations on the hard disk drive are written in a spatial sequence that matches the spatial sequence in which the storage locations on the production volume are written.

Abstract: Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected.

Abstract: A circuit, for managing operations for accessing a flash memory on the basis of requests received from a main CPU and from an auxiliary CPU, may be configured to: associate with the main CPU, a higher access priority to the flash memory than the access priority of the auxiliary CPU; command, in the absence of further requests for accessing the flash memory, the access to the flash memory for the main or auxiliary CPU which has initiated a first access request; verify, following a receipt of a second access request, the access priority associated with this second access request; suspend one of the first or the second access request having lower priority; and authorize the other of the first or the second access request having higher priority.

Abstract: A control apparatus includes first and second regions that each store device information of a monitoring target device; an evacuating region; and a processor configured to execute a procedure including: controlling switching between first and second states at a predetermined timing, the first state including the first region being in updatable and unreferenceable states and the second region being in referenceable and unupdatable states, the second state including opposite states to the first state; evacuating, in a case where the second region is being referred at a timing when the first state is switched to the second state, unreferred information stored in the second region to the evacuating region; controlling, after completion of evacuation, switching the state of the second region from referenceable to updatable; and controlling, after completion of reference to the unreferred information in the evacuating region, switching the state of the first region from updatable to referenceable.

Abstract: A method and system for improving tape drive memory storage is provided. The method includes receiving, by a storage tape drive, a data stream for storage. The data stream is passed through a non-volatile memory device (NVS2) of the storage tape drive. The data stream is divided into adjacent variable length data chunks and a chunk list file including similarity identifiers for each of the adjacent variable length data chunks is generated and stored within a (non-volatile memory device) NVS1. Duplicate data including duplicated data with respect to a group of data chunks of the adjacent variable length data chunks is identified and deleted from the NVS2 of the storage tape drive such that the group of data chunks remains within NVS2. The group of data chunks is written to a data storage tape cartridge. Pointers identifying each data chunk and an associated storage position are generated and stored.

Abstract: A method for execution by a dispersed storage and task (DST) execution unit includes generating a first compaction object by performing a compaction function on a first previously compacted object and first data slices that compare favorably to a cold access threshold. Storage of the first previously compacted object in a cold memory region is replaced with the first compacted object, and the first data slices are removed from prior storage in different memory regions. A second compacted object is generated by performing the compaction function on a second previously compacted object and second data slices that compare favorably to a hot access threshold. Storage of the second previously compacted object in a hot memory region is replaced with the second compacted object, and the second data slices are removed from prior storage in different memory regions.

Abstract: Prefetch apparatus and a method of prefetching are presented. The prefetch apparatus monitors access requests, each having an access request address, and has request tracking storage to store region entries for regions of memory space which each span multiple access request addresses. The request tracking storage keeps access information for access requests received in their corresponding region entries. When a new region access request is received, which belongs to a new region for which there is no region entry, and when the request tracking storage has an adjacent region entry for which the access information shows that at least a predetermined number of the access request addresses have been accessed, a page mode region prefetching process is initiated for all access request addresses in the new region.

Abstract: A memory system may include a memory device configured to store data received from a host; and a memory controller configured to, receive a received block of the data and a logical address associated with the data from the host, detect at least one halves of the received block as being duplicate halves based on whether a respective one of the at least one halves of the received block match one or more existing halves of stored blocks stored in the memory device, selectively store the at least one halves of the received block in the memory device based on whether the respective one of the at least one halves are duplicate halves such that the duplicate halves of the received block are not stored in the memory device, and store metadata associated with retrieving the received block.

Abstract: A system and a method of managing a plurality of storage tiers, may include: receiving a write-access request, including at least one data element for storage, a logical address associated with the data element and a tier identifier for a selected tier; computing a unique reference name based on the content of the data element, and associating the unique reference name with the logical address; using a global API to generate a first write-access command, that includes the unique reference name and the data element; customizing the write-access command according to an addressing scheme of the selected tier by a dedicated driver, to obtain at least one second write-access command; using the second write-access command to associate the unique reference name with at least one physical location on the selected tier; and storing the at least one data element at the associated at least one physical location.

Abstract: An integrated circuit comprising a plurality of last-level caches, a plurality of processor cores configured to access data in the plurality of last-level caches, and an interconnect network. The plurality of last-level caches can be placed in at least a high cache-power consumption mode and a low cache-power consumption mode. The plurality of last-level caches includes a first last-level cache and a second last-level cache. The interconnect network comprises a plurality of links that can be placed in at least a high link-power consumption mode and a low link-power consumption mode. The interconnect network is configured to cause a first subset of the plurality of links to be placed in the low link-power consumption mode based at least in part on the first last-level cache being in the low cache-power consumption mode.

Abstract: A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Abstract: An application programming interface (API), functioning as an interface between a storage controller and an owning application, is used to migrate, from a specified source LUN to a specified target LUN, at least one specified sub-LUN data chunk, the at least one specified sub-LUN data chunk having a predefined chunk size fixed by the storage controller. A specified total migration size is incrementally reduced by each completed migration of the at least one specified sub-LUN data chunk until the total migration size is zero and the migration is completed.

Abstract: Embodiment of a storage stack are disclosed whereby increased performance and other technical improvements are achieved by an application requesting access (e.g., asynchronously) to an address, returning a buffer, and the application issuing a buffer release when the operation is complete.

Abstract: Provided are an apparatus and method to cache data in a first memory that is stored in a second memory. At least one read-with-invalidate command is received to read and invalidate at least one portion of a cache line having modified data. The cache line having modified data is invalidated in response to receipt of read-with-invalidate commands for less than all of the portions of the cache line.

Abstract: Described are data movements techniques may include: receiving a plurality of write quotas for a plurality of physical media types; determining a first physical storage device of a first physical media type that is over utilized with respect to a write quota; selecting a first data portion of the first physical storage device for data movement; determining a target device that is not over utilized with respect to a write quota; determining an expected total write I/O workload of the target device after hypothetically moving the first data portion thereto; determining whether the expected total write I/O workload exceeds a write quota of the target device; and responsive to determining the total write I/O workload does not exceed the write quota for the target device, moving the first data portion to the target storage device.

Abstract: The present disclosure is concerned with improvements to cache systems that can be used to improve the performance (e.g. hit performance) and/or bandwidth within a memory hierarchy. For instance, a data processing apparatus is provided that comprises a cache. Access circuitry receives one or more requests for data and when the data is present in the cache the data is returned. Retrieval circuitry retrieves the data and stores the data in the cache, either proactively or in response to the one or more requests for the data. Control circuitry evicts the data from the cache and, in dependence on at least one condition, stores the data in the further cache. The at least one condition comprises a requirement that the data was stored into the cache proactively and that a number of the one or more requests is above a threshold value.

Abstract: A processing system tracks counts of accesses to memory pages using a set of counters located at the memory module that stores the pages, wherein the counts are adjusted at least in part based on refreshes of the memory pages. This approach allows a processing system to efficiently maintain the counts with relatively small counters and with relatively low overhead. Furthermore, the rate at which the counters are adjusted, relative to the page refreshes, is adjustable, so that the access counts are useful for a wide variety of application types.