Abstract: Systems and methods are disclosed for virtualized caches. For example, an integrated circuit (e.g., a processor) for executing instructions includes a virtually indexed physically tagged first-level (L1) cache configured to output to an outer memory system one or more bits of a virtual index of a cache access as one or more bits of a requestor identifier. For example, the L1 cache may be configured to operate as multiple logical L1 caches with a cache way of a size less than or equal to a virtual memory page size. For example, the integrated circuit may include an L2 cache of the outer memory system that is configured to receive the requestor identifier and implement a cache coherency protocol to disambiguate an L1 synonym occurring in multiple portions of the virtually indexed physically tagged L1 cache associated with different requestor identifier values.

Abstract: A storage system and method for dynamic selection of a host interface are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive, from a host, a selection of a first host interface; in response to receiving the selection of the first host interface, implement the first host interface; after the first host interface has been implemented, receive, from the host, a selection of a second host interface; and in response to receiving the selection of the second host interface, implement the second host interface even though the first host interface was previously implemented. Other embodiments are provided.

Abstract: Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected.

Abstract: A memory system includes: a controller including first and second cores; a plurality of channels connected to the controller; a plurality of first memory devices each including first memory blocks allocated to the first core, each of the plurality of channels being coupled to at least one first memory device; and a plurality of second memory devices each including second memory blocks allocated to the second core, each of the plurality of channels being coupled to at least one second memory device, wherein the controller further includes: a global wear leveling manager configured to perform a global wear leveling operation by swapping a first memory block and a second memory block, which are connected to the same channel among the first memory blocks and the second memory blocks, between the first and second cores on the basis of wear levels of the first memory blocks and the second memory blocks.

Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first storage region and a second storage region. The memory controller comprises a third storage region storing a master table and a fourth storage region storing a change history of the master table. The memory controller is configured to: order the nonvolatile memory to write the master table stored in the third storage region in the first storage region when receiving a power-off command from outside; order the nonvolatile memory to write the change history stored in the fourth storage region in the second storage region.

Abstract: A method and system for communication between a flash memory controller and a nonvolatile memory. When a controller and all devices on a given channel are all set to be in a traditional mode, the controller and all the devices on the given channel are operated in the traditional mode; and when the controller and all the devices on the given channel are all set to be operated in a PAM mode, at a valid data transmission phase, the controller can send a command to a plurality of logical units on the same channel, and the plurality of logic units can return the command and/or a state on the same channel.

Abstract: A storage device includes a nonvolatile memory device including a plurality of nonvolatile memories; a controller configured to allocate write blocks of the nonvolatile memory device to a plurality of streams provided from an outside; and a buffer memory configured to store a result of allocation of the write blocks to the plurality of streams, wherein the controller is further configured to reallocate the write blocks of the nonvolatile memory device to the plurality of streams based on the result of allocation stored in the buffer memory.

Abstract: Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

Abstract: A data storage device and method for enabling a compare command with built-in data transformations. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to: receive, from a host, a compare command, a logical block address, data, and an instruction to perform a data transformation operation; read data from a location in the memory corresponding to the logical block address; execute the data transformation operation on the data read from the location in the memory; and compare a result of the data transformation operation with the data received from the host. Other embodiments are provided.

Abstract: Various embodiments enable sending a notification to a host system based on an address mapping entry miss (or mismatch) on a memory sub-system, which can facilitate an update of one or more address mapping entries stored on the host system.

Abstract: In one set of embodiments, a computer system can periodically run an unmap service configured to scan a subset of bitmaps maintained by a file system of the computer system. As part of scanning each bitmap in the subset, the unmap service can, for each bit in the bitmap: (1) check whether the bit indicates that a corresponding physical block address (PBA) on the storage backend is currently free; (2) upon determining that the bit indicates the PBA is currently free, identify an extent within the bitmap where the PBA resides; (3) check whether an unmap indicator associated with the extent indicates that at least one free PBA in the extent is not currently unmapped in the storage backend; and (4) upon determining that the unmap indicator indicates at least one free PBA in the extent is not currently unmapped in the storage backend, add the PBA to a list of PBAs to be unmapped.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a first temperature level of a first block family associated with a memory device; identify a second temperature level of a second block family associated with the memory device; determine if a condition is satisfied based on the first temperature level and the second temperature level; and in response to the condition being satisfied, combine the first block family and the second block family to generate a combined block family.

Abstract: An operating method of a memory system may include: searching for, in a memory, target map data corresponding to the read request; loading the target map data from a memory device when the target map data are not searched; compressing the loaded target map data using a predetermined compression ratio depending on an available capacity of the memory; caching the compressed target map data in the memory; parsing the compressed target map data; reading target user data corresponding to the read request from the memory device based on the parsed target map data; and outputting the read target user data.

Abstract: Apparatuses and methods for performing buffer operations in memory are provided. An example apparatus can include an array of memory cells, a page buffer, and a controller. The page buffer can be configured to store a number of pages of data in respective caches of the page buffer. The controller can be configured to program the number of pages of data to a first group of cells in the array. The programming operation can include programming the first group of cells to target states encoded with respective data patterns. The programming operation can include incrementally releasing a first of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular first one of the target states.

Abstract: The present disclosure generally relates to thermal throttling a nonvolatile memory device in a data storage device. Nonvolatile memory devices can sustain higher temperatures for a limited duration of time as part of the lifecycle/operation of the device. By allowing for a small margin of time at a higher temperature of operation, the maximum capability of the data storage device is increased. In so doing, the data storage device reliability can be maintained while increasing the device performance.

Abstract: A printing apparatus includes a non-volatile memory and a management unit that performs management in a case of using the non-volatile memory as a spool buffer for print data. The management unit includes a first derivation unit that derives a first life time consumption rate of the non-volatile memory based on the cumulative number of printed sheets of print media printed with a printing unit, and a second derivation unit that derives a second life time consumption rate of the non-volatile memory based on the number of times of rewriting operations of the non-volatile memory. The management unit controls a capacity allocated to a spool buffer to be defined in the non-volatile memory based on a result of comparison between the second life time consumption rate and the first life time consumption rate.

Abstract: A memory block of a non-volatile memory device is identified. The memory block has a first region and a second region, where a storage density of the first region is larger than the second region. Data is programmed at the first region of the memory block. An attribute of the memory block based on a sensor is received during programming of the data at the memory block. The attribute characterizes the data being programmed at the first region. The attribute is stored at a volatile during programming of the data at the memory block. The attribute is stored on a memory page of the second region responsive to the programming of the data at the first region being complete.

Abstract: Methods, systems, and devices for host side memory address management are described. In some examples, a host system may identify a read request that includes a logical address of a block of a memory device. The read request may be associated with a descriptor indicating a page of a cache of the host system. The host system may determine to assign a descriptor to a page of the cache, and may recycle one or more pages of the cache. In some examples, the host system may determine whether the page indicated by the descriptor includes a mapping between the logical address and a physical address of the memory device, and may issue a read command to the memory device based on the page including the mapping.

Abstract: In a method for dynamic wear-levelling and load redirection in a solid-state drive (SSD) including one or more blocks, the method including: receiving, by a controller, a request to write data; calculating, by the controller, a vulnerability factor of the one or more blocks; selecting, by the controller, a target block from the one or more blocks to receive the request to write data; determining, by the controller, a status of the target block based on the vulnerability factor of the target block; writing, by the controller, the data to the target block based on the status of the target block; and updating, by the controller, a mapping table based on the data written to the target block.

Abstract: A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.