Patents Examined by Khai M. Nguyen
  • Patent number: 11581896
    Abstract: An analog-to-digital converter includes: a voltage-current converter receiving an analog input voltage, generating a first digital signal from the analog input voltage, and outputting a residual current remaining after the first digital signal; a current-time converter converting the residual current into a current time in a time domain; and a time-digital converter receiving the residual time, and generating a second digital signal from the residual time, wherein the first digital signal and the second digital signal are sequences of digital codes representing respective signal levels of the analog input voltage.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: February 14, 2023
    Assignee: SAMSUNG ELECTORNICS CO., LTD.
    Inventors: Kyoungjun Moon, Dongryeol Oh, Youngjae Cho, Michael Choi
  • Patent number: 11575979
    Abstract: Systems and methods for monitoring and detecting parameters within a facility. The systems and methods include an actuator to adjust a position of a sensor device, the sensor device capable of gathering sensor data related to one or more parameters. The sensor device is in communication with a transmitter to transmit sensor data, a horizontal position, and a vertical position of the sensor device as it moves and gathers the sensor data. The data is assembled into a data structure showing the data throughout the facility for identification of abnormalities and adjustment of facility parameters.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: February 7, 2023
    Assignee: Amazon Technologies, Inc.
    Inventor: Gianluca Grilli
  • Patent number: 11569840
    Abstract: An analog to digital converter (ADC) that is configured to service a photo-diode includes a capacitor and a self-referenced latched comparator. The capacitor produces a photo-diode voltage based on charging by a photo-diode current associated with the photo-diode and a digital to analog converter (DAC) source current and/or a DAC sink current. The self-referenced latched comparator generates a first digital signal that is based on a difference between the photo-diode voltage and a threshold voltage associated with the self-referenced latched comparator. Also, one or more processing modules executes operational instructions to process the first digital signal to generate a second digital signal and/or a third digital signal. An N-bit DAC generates the DAC source current based on the second digital signal, and an M-bit DAC generates the DAC sink current based on the third digital signal. The DAC source current and/or the DAC sink current tracks the photo-diode current.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: January 31, 2023
    Assignee: SigmaSense, LLC.
    Inventor: Phuong Huynh
  • Patent number: 11569841
    Abstract: Partition information associated with one or more partitions that divide a range of values into at least a higher and lower set of values is received. An uncompressed value that falls within the range of values is received and a compressed value that includes a set indicator and intra-set information is generated using the uncompressed value. This includes generating the set indicator based at least in part on whether the uncompressed value falls in the higher or lower set of values, determining whether the uncompressed value includes an extraneous bit where it is necessary but not sufficient that the uncompressed value fall in the higher set of values for the uncompressed value to include the extraneous bit, and generating the intra-set information, including by: excluding the extraneous bit in the uncompressed value from the intra-set information if it is determined to be included. The compressed value is output.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: January 31, 2023
    Inventor: Yingquan Wu
  • Patent number: 11569828
    Abstract: An analog to digital converter (ADC) senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. The digital output signal provided to the N-bit DAC is an inverse function of the load current. The ADC is operative to sense very low currents (e.g., currents as low as is of pico-amps) and consume very little power (e.g., less than 2 ?W).
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: January 31, 2023
    Assignee: SigmaSense, LLC.
    Inventor: Phuong Huynh
  • Patent number: 11569832
    Abstract: An apparatus is disclosed for analog-to-digital conversion. In an example aspect, the apparatus includes an analog-to-digital converter (ADC). The ADC includes a reference-crossing detector having an input and an output. The ADC also includes a ramp generator coupled between the output of the reference-crossing detector and the input of the reference-crossing detector. The ADC further includes a voltage shifter coupled between the output of the reference-crossing detector and the input of the reference-crossing detector.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: January 31, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Aram Akhavan, Seyed Arash Mirhaj, Lei Sun, Elias Dagher
  • Patent number: 11567163
    Abstract: A mobile computing device includes: a tracking sensor; a proximity sensor; and a controller coupled to the tracking sensor and the proximity sensor, the controller configured to: obtain a sequence of sensor datasets, each sensor dataset including: (i) a location of the mobile computing device, in a local coordinate system, generated using the tracking sensor, (ii) a proximity indicator generated using the proximity sensor, defining a range to a fixed reference device, and (iii) a predefined location of the reference device in a facility coordinate system; determine, from the sequence, an adjusted pose of an origin of the local coordinate system in the facility coordinate system; and generate, using a current location of the mobile device in the local coordinate system and the adjusted pose, a corrected location of the mobile computing device in the facility coordinate system; and execute a control action based on the corrected location.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: January 31, 2023
    Assignee: Zebra Technologies Corporation
    Inventor: Patrenahalli M. Narendra
  • Patent number: 11568758
    Abstract: A terminal is disclosed. The terminal according to an embodiment of the present invention comprises: an output unit for outputting a notification; a storage unit for storing a database; a control unit for controlling the outputting of the notification; and an artificial intelligence unit for acquiring information regarding a user's context, and outputting a notification when the user's context corresponds to information included in the database, wherein the database includes at least one of a user's personal database, a standard activity database, and an accident type database.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: January 31, 2023
    Assignee: LG ELECTRONICS INC.
    Inventors: Eunjoo Rhee, Choil Lee
  • Patent number: 11563438
    Abstract: An A/D conversion circuit includes a comparison-reference-signal generator section configured to generate a comparison reference signal synchronized with a sampling clock signal, a comparator configured to compare a voltage of an input signal and a voltage of the comparison reference signal to thereby generate a trigger signal, a time to digital converter configured to calculate a first time digital value, and a digital-signal generator section configured to generate, based on the first time digital value and a second time digital value, a digital signal corresponding to the voltage of the input signal.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: January 24, 2023
    Inventor: Masayoshi Todorokihara
  • Patent number: 11563443
    Abstract: A latch circuit sequentially latches a first data weighted averaging (DWA) data word and then a second DWA data word. A first detector circuit identifies a first bit location in the first DWA data that is associated with an ending of a first string of logic 1 bits in the first DWA data word. A second detector circuit identifies a second bit location in the second DWA data word associated with an ending of a second string of logic 1 bits in the second DWA data word. A DWA-to-binary conversion circuit converts the second DWA data word to a binary word by using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word. A binary value for that binary word that is equal to the identified number is output.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: January 24, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Rupesh Singh
  • Patent number: 11556785
    Abstract: An apparatus identifies partial tensor data that contributes to machine learning using tensor data in a tensor format obtained by transforming training data having a graph structure. Based on the partial tensor data and the training data, the apparatus generates expanded training data to be used in the machine learning by expanding the training data.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: January 17, 2023
    Assignee: FUJITSU LIMITED
    Inventors: Shotaro Yano, Takuya Nishino, Koji Maruhashi
  • Patent number: 11552646
    Abstract: A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: January 10, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Vikram Singh
  • Patent number: 11547874
    Abstract: Systems and techniques may be used to estimate a patient state during a radiotherapy treatment. For example, a method may include generating a dictionary of expanded potential patient measurements and corresponding potential patient states using a preliminary motion model. The method may include training, using a machine learning technique, a correspondence motion model relating an input patient measurement to an output patient state using the dictionary. The method may include estimating, using a processor, the patient state corresponding to an input image using the correspondence motion model.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: January 10, 2023
    Assignee: Elekta, Inc.
    Inventors: Martin Emile Lachaine, Silvain Beriault
  • Patent number: 11545991
    Abstract: Disclosed herein are some examples of analog-to-digital converters (ADCs) that can perform auto-zeroing with amplifying a signal for improvement of a signal-to-noise ratio. The ADCs may produce a first digital code to represent an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to produce a digital output code to represent the analog input signal. The ADC may utilize a first observation and a second observation of an analog residue value representing the residue to produce the second digital code.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: January 3, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Jesper Steensgaard-Madsen, Andrew J. Thomas
  • Patent number: 11546808
    Abstract: A first base station receives, from a second base station, a message comprising at least one parameter of a first cell of the second base station. The at least one parameter indicates that the first cell supports at least one vehicle-to-everything (V2X) service. A handover decision for a wireless device is made. The first base station sends, to the second base station, a handover request for the wireless device based on the handover decision and the message.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: January 3, 2023
    Assignee: Ofinno, LLC
    Inventors: Kyungmin Park, Esmael Dinan
  • Patent number: 11544852
    Abstract: A performance scanning system that operates to detect and measure surface parameters of a portion of an athlete and uses the surface parameters to determine the likelihood that the athlete's physical performance has been or will be impaired.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: January 3, 2023
    Inventors: Paul E. Thomson, Mark F. Smith
  • Patent number: 11537853
    Abstract: Described herein is a neural network accelerator (NNA) with a decompression unit that can be configured to perform multiple types of decompression. The decompression may include a separate subunit for each decompression type. The subunits can be coupled to form a pipeline in which partially decompressed results generated by one subunit are input for further decompression by another subunit. Depending on which types of compression were applied to incoming data, any number of the subunits may be used to produce a decompressed output. In some embodiments, the decompression unit is configured to decompress data that has been compressed using a zero value compression scheme, a shared value compression scheme, or both. The NNA can also include a compression unit implemented in a manner similar to that of the decompression unit.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 27, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Tariq Afzal, Arvind Mandhani
  • Patent number: 11532074
    Abstract: A method is for providing a resultant image dataset for a volume of interest. In an embodiment, an X-ray image dataset for the volume of interest is received, having a first noise level. A trained generator function is received, a parameter of which is based on a first and a second training image dataset for a training volume of interest. The first and the second training image dataset include a first training noise level. In addition, a resultant image dataset for the volume of interest is determined by applying the trained generator function to input data comprising the X-ray image dataset, the resultant image dataset has a second noise level less than the first noise level. In addition, the resultant image dataset is provided. As such, a higher noise level can be accepted and/or a lower X-ray dose can be used in the acquisition of the X-ray image dataset.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: December 20, 2022
    Assignee: Siemens Healthcare GmbH
    Inventors: Christian Kaethner, Sai Gokul Hariharan
  • Patent number: 11528032
    Abstract: Device for generating analogue signals comprises a digital-to-analogue converter comprising at least one digital input and one analogue output, a circuit for generating a first clock signal of frequency fs, and a digital register configured so as to receive at the input and to store N bits representative of an analogue output signal of the converter, N being an integer greater than or equal to 1, and for receiving the first clock signal, the register comprising, for each bit, two complementary digital outputs.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: December 13, 2022
    Assignee: TELEDYNE E2V SEMICONDUCTORS SAS
    Inventor: Grégory Wagner
  • Patent number: 11528645
    Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. According to the disclosure, a base station may configure serving cells having different frame start time points, using carrier aggregation (CA), for operation of a terminal, and thus can increase the transmission rate of the terminal.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: December 13, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehyuk Jang, Soenghun Kim, Anil Agiwal