Abstract: The technology disclosed assigns quality scores to bases called by a neural network-based base caller by (i) quantizing classification scores of predicted base calls produced by the neural network-based base caller in response to processing training data during training, (ii) selecting a set of quantized classification scores, (iii) for each quantized classification score in the set, determining a base calling error rate by comparing its predicted base calls to corresponding ground truth base calls, (iv) determining a fit between the quantized classification scores and their base calling error rates, and (v) correlating the quality scores to the quantized classification scores based on the fit.

Abstract: An A/D converter includes an A/D conversion unit and an output unit. The A/D conversion unit includes a second A/D converter (successive approximation register A/D converter) and generates first digital data having a first number of bits and second digital data having a second number of bits, where the second number of bits is smaller than the first number of bits. The output unit provides first output information that is the first digital data and also provides second output information based on the second digital data. The output unit provides the second output information before providing the first output information.

Abstract: One or more embodiments of a successive approximation type analog-to-digital converter that converts an analog input into a digital conversion value and outputs the digital conversion value, may include: a capacitance DAC that generates a bit-by-bit potential based on an analog input; a comparator that compares the potential generated by the capacitance DAC, wherein the comparator is a memory cell rewriting type, the comparator includes a first stage current mirror type operational amplifier; and a second stage memory cell; a conversion data generator that generates conversion data of resolution bits based on a comparison result of the comparator; and a correction circuit that corrects an output error of the conversion data caused by an offset error of the comparator by adding or subtracting an offset correction value that is a fixed value, and outputs the conversion data as a digital conversion value.

Abstract: Some embodiments of the disclosure provide an artificial neural network system for recognizing a lesion in a fundus image. The system includes a pre-processing module configured to pre-process a target fundus image and a reference fundus image taken from one person separately, a first neural network (12) configured to generate a first advanced feature set from the target fundus image, a second neural network (22) configured to generate a second advanced feature set from the reference fundus image, a feature combination module (13) configured to combine the first advanced feature set and the second advanced feature set to form a feature combination set, and a third neural network (14) configured to generate, according to the feature combination set, a judgmental result of lesions.

Abstract: Representative embodiments are disclosed for a rapid and highly parallel decompression of compressed executable and other files, such as executable files for operating systems and applications, having compressed blocks including run length encoded (“RLE”) data having data-dependent references. An exemplary embodiment includes a plurality of processors or processor cores to identify a start or end of each compressed block; to partially decompress, in parallel, a selected compressed block into independent data, dependent (RLE) data, and linked dependent (RLE) data; to sequence the independent data, dependent (RLE) data, and linked dependent (RLE) data from a plurality of partial decompressions of a plurality of compressed blocks, to obtain data specified by the dependent (RLE) data and linked dependent (RLE) data, and to insert the obtained data into a corresponding location in an uncompressed file.

Abstract: Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.

Abstract: An analog-to-digital converter, configured to convert an input signal into an n bits digital output signal, includes a capacitor module, a control signal generation unit, a comparator, and a register. The capacitor module is configured to receive the input signal at a sampling phase in a normal mode, and to generate a first sampling signal and a second sampling signal according to the input signal in a conversion phase. The control signal generation unit is configured to adjust the first sampling signal or the second sampling signal in the conversion phase. In the normal mode, the comparator is configured to compare the first sampling signal and the second sampling signal in the conversion phase to generate n comparison signals. The register is configured to store the n comparison signals as the digital output signal, and output the digital output signal in the normal mode.

Abstract: An apparatus, method and computer program for a mobile transceiver and for a base station transceiver. The method includes receiving a downlink signal from a base station transceiver of the mobile communication system via a downlink data channel, identifying a line of sight component of at least the first positioning symbol of the downlink signal based on the one or more sequences of zero-value samples and determining information related to a location of the mobile transceiver based on the one or more non-zero-value samples received within the line of sight component of the first positioning symbol. The downlink signal includes one or more positioning symbols having a first positioning symbol, wherein the first positioning symbol is based on samples in a time domain to be transmitted by the base station transceiver.

Abstract: Examples relate to an optical imaging system, and to a corresponding apparatus, method and computer program for an optical imaging system. The optical imaging system comprises one or more information sources for providing information about a current orientation of the optical imaging system towards at least a part of an object of interest. The optical imaging system comprises one or more output modules for providing guidance information for a user of the optical imaging system. The optical imaging system comprises a processing module configured to determine information on a desired orientation of the optical imaging system towards at least a part of the object of interest.

Abstract: Disclosed herein are antenna boards, antenna modules, and communication devices. For example, in some embodiments, an antenna module may include: an antenna patch support including a flexible portion; an integrated circuit (IC) package coupled to the antenna patch support; and an antenna patch coupled to the antenna patch support.

Abstract: Techniques related to managing data communications between devices are described. In an example, a computer system receives, from a first device, a request to transfer a communications session with the first device and a second device. The computer system determines contextual data associated with the communications session. Using at least the contextual data, the computer system determines the communications session is permitted to be transferred from the first device to a third device based. The computer system causes a transferred communications session to be established with the third device and the second device.

Abstract: The present disclosure relates to circuitry comprising: digital circuitry configured to generate a digital output signal; and monitoring circuitry configured to monitor a supply voltage to the digital circuitry and to output a control signal for controlling operation of the digital circuitry, wherein the control signal is based on the supply voltage.

Abstract: One or more computer processors detect an unregistered device associated with an identified location, wherein the unregistered device is associated with wireless behavior. The one or more computer processors identify one or more registered devices in a proximity to the identified location and the detected unregistered device. The one or more computer processors identify an occupant associated with the detected unregistered device utilizing a trained device identification model, the identified location, and respective wireless behavior associated with the detected unregistered device and the identified one or more registered devices.

Abstract: A method for adjusting a wireless modem includes: a channel parameter of a wireless modem at a present moment is acquired; a target clock frequency and a target working voltage of the wireless modem are generated, according to the channel parameter, with a neural network that is pre-trained; and a working voltage and a clock frequency of the wireless modem are adjusted to the target working voltage and the target clock frequency, respectively.

Abstract: The kernel function generation unit 81 defines a first kernel function by using two-dimensional feature representation that represents a combination of two features of data. The model learning unit 82 defines a linear model including an inner product of a mapping used in the first kernel function and a first weight and performs learning with the defined linear model. The component expanding unit 83 expands the learned linear model to define expanded component representation that is new component representation of the data. The expansion model generation unit 84 generates an expansion model including an inner product of data by the expanded component representation and a second weight.

Abstract: A successive-approximation register analog-to-digital converter (SAR ADC), a correction method and a correction system are provided. The SAR ADC generates an original weight value sequence according to multiple original weight values. The SAR ADC converts an analog time-varying signal to establish a transforming curve corresponding to the original weight values. In addition, the SAR ADC generates an offset value sequence according to an offset of the transforming curve, uses the offset value sequence to correct the original weight value sequence to generate a corrected weight value sequence, and uses multiple corrected weight values of the corrected weight sequence to improve linearity of the transforming curve.

Abstract: A successive-approximation analog-to-digital converter includes a sampling circuit for sampling an analog input signal to acquire a sampled voltage, and a regenerative comparator for comparing the sampled voltage with a succession of reference voltages to generate, for each reference voltage, a decision bit indicating the comparison result. The converter also includes a digital-to-analog converter which is adapted to generate the succession of reference voltages, in dependence on successive comparison results in the comparator, to progressively approximate the sampled voltage. The regenerative comparator comprises an integration circuit for generating output signals defining the decision bits, and a plurality of regeneration circuits for receiving these output signals. The regeneration circuits are operable, in response to respective control signals, to store respective decision bits defined by successive output signals from the integration circuit.

Abstract: A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

Abstract: An automated system includes transducers, at least one computing device, and at least one automated apparatus. The transducer(s) is/are driven and sensed using drive-sense circuit(s). A drives and senses drive and sense a transducer via a single line, generates a digital signal representative of a sensed analog feature to which the transducer is exposed, and transmits the digital signal to the computing device. The computing device receives digital signals from at least some of drive-sense circuits and process them in accordance with the automation process to produce an automated process command. The automated apparatus executes a portion of an automated process based on the automated process command.

Abstract: A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100 s of kHz (e.g., 200-300 kHz), or even higher.