Abstract: An adaptive sigma delta modulator has an input stage, a conventional sigma delta modulator, and adaptation stage, and an output stage. The input stage produces a difference signal representing the difference between an analog input signal and an adaptive signal, the amplitude of the analog input signal being in a first range [−a +a]. The conventional sigma delta modulator produces an intermediate digital output sequence representative of the difference signal, the amplitude of the intermediate digital output sequence being in a second range [−b +b], wherein b<a. The adaptation stage produces the adaptive feedback signal such that the amplitude of the adaptive signal keeps the difference signal within the second range [−b +b].

Abstract: A method of converting an analog signal to a digital signal includes (a) filtering the analog signal to the range 0≦fx≦fB; (b) sampling the filtered signal at a rate fS>>fN, where fS is the sampling frequency, fN=2fx is the Nyquist frequency of the sampled signal, and fB≦fS/2 is the constrained signal bandwidth; (c) converting the sampled signal to an optical sampled signal: (d) converting the optical sampled signal from a temporal signal to a spatial signal; (e) illuminating a smart pixel array with the spatial signal; (f) processing the spatial signal with an error diffusion neural network to produce a 2-D binary image; and (g) averaging rows and columns of the 2-D binary image using a digital low pass filter and a decimation circuit.

Abstract: A digital-to-analog converter containing one or more ideal stages, a reduced-radix stage coupled with the one or more ideal stages, and a digital calibration logic section to operate on a calibration value. The calibration value is the difference between a first calibration constant and a second calibration constant. Digital input codes are received through the digital logic section. The calibration value is added to digital input codes with values that exceed the value of the second calibration constant. The outputs of the digital logic section are input to all stages of the digital-to-analog converter.

Abstract: A digital signal directed to a display (e.g., a plurality of display elements forming an array of display elements) may be converted into an analog signal using a nonlinear relationship. In one embodiment, a drive signal may be provided to at least one display element of the array of display elements in response to calibration data. Embedding the calibration data using the nonlinear relationship, the amplitude of the drive signal may be determined in order to control a perceptible output from the at least one display element of the array of display elements. Thus, a compensation for initial non-uniformity degradation over time, and/or non-uniform degradation may be provided to the at least one display element of the array of display elements. The nonlinear relationship reduces the number of discrete calibration data levels required to avoid perceptible contrast among neighboring pixels that leads to contouring effects.

Abstract: An A/D conversion system for an image sensor. The image sensor acquires image signals, and outputs them to a plurality of sample and hold circuits. The sample and hold circuits are grouped and are commonly actuated, in order to simplify the control circuit. Once the signals are in the sample and hold circuits, the next clock cycle commonly actuates a plurality of A/D converters which commonly convert all of those signals. During that same clock cycle, another set of sample and hold circuits may be actuated.

Abstract: An electric noise absorber for preventing looseness of magnetic body parts in a closed housing, without increasing the number of parts or decreasing the strength of the housing. The housing comprises a pair of case halves which house ferrite core halves, respectively, and are hinged to each other. The bottom wall of each case half is formed with a curved shape convex toward the space housing the ferrite core half. When the case halves are closed with the ferrite cores therein, the ferrite cores press each other toward respective bottom walls and resiliently deform the walls. The resilience of the deformed bottom walls urges abutting surfaces of the ferrite cores into close contact.

Abstract: A method and apparatus for performing gain calibration of an analog to digital converter is provided. During a calibration mode, an input sampling circuit comprised of multiple branches can be configured to provide a calibration mode gain of one. The analog-to-digital converter selects one of the parallel capacitor input sampling branches and repetitively samples the whole charge associated with the calibration voltage signal. This sampling step is repeated for each input sampling branch that is used during normal operation mode. The results of the sampling of the branches may be suitably averaged to create a gain calibration coefficient that is representative of and accounts for sampling variations between the input branches.

Abstract: A digital-to-analog (D/A) converter with a required accuracy can be implemented in a smaller chip area and at a lower cost. The D/A converter comprises a decoder which receives a digital input signal comprised of a first number of bits, and divides the first number of bits into a second number of bit groups. Bit group converters equal in number to the second number, are provided for the second number of bit groups, and each selects and uses a form of weight for each of the bit groups associated therewith to convert the bit group into an analog form in response to the second number of bit groups, thereby generating the second number of bit group analog outputs. An adder adds the second number of the bit group analog outputs to form an analog signal output representative of the digital signal input.

Abstract: A method and apparatus to encode data is provided. The method includes the steps of: i) dividing the data into a plurality of blocks, with each block having a plurality of bits, wherein the plurality of blocks includes a first subset of blocks and a second subset of blocks; ii) encoding data in the first subset; arranging a codeword to include the encoded data of the first subset and the second subset; iii) scanning a plurality of segments in the codeword for at least one predetermined sequence; and iv) encoding a scanned segment when the predetermined sequence is found in the segment. A method and apparatus to decode data is also provided according to the present invention.

Abstract: A successive-approximation analog-digital converter including a logic control circuit timed by means of an external clock signal clock. The logic control circuit includes a register containing a first digital signal formed of N bits, which is the product of a first analog-digital conversion. The logic control circuit is suitable for producing a second digital signal formed of N bits through a second analog-digital conversion in N clock cycles. This analog-digital converter converts the second digital signal sent by the logic circuit to a second analog signal. A comparator compares the first analog signal with the second analog signal which has been input to the analog-digital converter.

Abstract: A multiple-bit digital attenuator with improved frequency response and reduced insertion loss characteristics is provided. The multiple-bit digital attenuator comprises at least one 2-bit digital attenuator. The 2-bit digital attenuator includes a single series switching transistor located between a first terminal and a second terminal and controllable by a reference control signal, a temperature compensation circuit placed in parallel with the series switching transistor and including two temperature compensation transistors, a pair of first shunt circuits located at the first and second terminals and controllable by a first bit control signal, and a second shunt circuit located between the two temperature compensation transistors and controllable by a second bit control signal.

Abstract: A CDAC circuit is provided that can operate at low supply voltages, for example, at supply voltages of 2.5 volts or less. To accomplish low voltage operation, switches in the CDAC circuit, such as sampling bit switches, mid-point switches or auto-zero switches, are gate-boosted to permit the voltage at the transmission gates to exceed the threshold voltage and thus permit the transmission gates to effectively operate. As a result, the CDAC can continue to operate, even with the existence of lower power supply voltages. In accordance with an exemplary embodiment, a gate-boosting circuit comprises a pair of N-channel transistor devices and a charging capacitor configured to provide a gate-boosting voltage to the transmission gates. In addition, the gate boosting circuit can comprise conventional CMOS devices, rather than more expensive low threshold MOSFET devices.

Abstract: According to an embodiment of the present invention, an input signal is provided to an oscillator, which creates a count signal with a greater frequency than the input signal. The input signal triggers the oscillator to oscillate depending on the value of the input signal. The oscillator output is provided to a counter, which counts the number of oscillations undergone by the oscillator during a single period of the input signal or a number of periods of the input signal, whichever is desired. Since the oscillator frequency is greater than the frequency of the input signal, the oscillator effectively acts like a clock to time the input signal; the counter effectively acts to record the ‘time’ measured by the oscillator (clock). More formally, the counter generates a count value based upon the width of the input signal pulses. The counter output is provided to a decoder, which interprets the count generated by the counter.

Abstract: A digital to analog converter is provided. The converter includes a multi-bit counter, a first and a second plurality of logic gates coupled to the multi-bit counter, a digital input selectively coupled to the first and second plurality of logic gates. The converter further includes a first AND gate coupled to an output of the first plurality of logic gates and a second AND gate coupled to an output of the second plurality of logic gates. In addition, the converter includes a clock coupled to an input of the first and second AND gates and an input of the multi-bit counter and a filter coupled to an output of the first and second AND gates, wherein the filter includes an output for an analog signal based on the digital input.

Abstract: This invention relates generally to methods and apparatuses for implementing cyclic return to zero techniques for digital to analog (D/A) conversion. Generally, embodiments of the invention disclose techniques for generating low-distortion continuous-time output waveforms in digital-to-analog converters (DACs) wherein the transient errors are not correlated with the DAC input signal, thereby resulting in DACs with significantly reduced nonlinear distortion. In one embodiment, a cyclic return to zero (CRTZ) digital to analog converter (DAC) includes at least two return to zero (RTZ) signal generating circuits, e.g. RTZ sub-DACs, to perform D/A conversion and a cycler, e.g. an RTZ sub-DAC cycler, to cycle between the two RTZ sub-DACs. The RTZ sub-DAC cycler cycles between the two RTZ sub-DACs such that one of the RTZ sub-DACs is active to perform D/A conversion for at least an entire sample period while the other RTZ sub-DAC is inactive.

Abstract: For the realization of a unipolar analog input range, in addition to the provision of an analog input sampling circuit having an input capacitor, a charge transfer circuit, an integrator having an integrating capacitor, a comparator, and a D-type flip-flop, there is further provided a reference voltage sampling circuit for selectively adding either of a subtraction and addition voltages which are different from each other to a sampled analog input voltage in response to a delayed comparator output. The reference voltage sampling circuit has a subtraction and addition capacitors differing in capacitance value from each other.

Abstract: In this invention a thirty three bit word is encoded from a thirty two bit word to conform to RLL coding constraints. A parity bit is added to the coded word after coding is complete. With the parity bit inserted the code satisfies a minimum Hamming weight of nine and no more than eleven consecutive zeros and no more than eleven consecutive zeros in both the odd and even interleaves. A table of “bad” eight bit sequences is used to compare the odd and even interleaves of the right and left halves of the input word that is being encoded. If a “bad” sequence is found, its position in the table points to a second table containing a four bit replacement code that is inserted into the coded output word. Flag bits in the output coded word are set to indicate the violation of the coding constraints and provide a means by which a decoder can be used to reverse the process and obtain the original input word.

Abstract: A digital to analog converter includes a network of impedance components having a plurality of nodes having associated voltages. A tap is coupled to one or more associated one of the plurality of nodes to source or sink electrical current relative to the associated node(s). A switching system is operative to couple a selected one of the nodes to an output according to a digital input word and thereby provide an analog voltage corresponding to the digital input.

Abstract: A method of modulating and a method of demodulating for a run length limited (RLL) code having an improved direct current (DC) suppression capability. Received data is modulated using a DC suppression control code group which is separate from a data modulation conversion code group. The DC suppression control code group maximizes use of the characteristics of codewords in conversion code groups, such as, the sign of parameter CSV representing the DC value within a codeword and the characteristics of parameter INV predicting the DSV transition direction of the next codeword, while relaxing the redundant codeword generation condition or the condition of usable codewords compared with the data modulation conversion code group. Therefore, the number of codewords increases, so that the probability of DC suppression control further increases.

Abstract: A switched-capacitor digital-to-analog converter circuit is disclosed. The switched-capacitor digital-to-analog converter circuit includes crossing switches for each capacitor branch, the crossing switches are used to eliminate cross interference between digital-to-analog converter blocks sharing the same reference voltages.